On the public citation graph
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jpdc.1994.1086openalex-snapshot
Dynamic Reconfiguration of Optically Interconnected Networks with Time-Division Multiplexing
inferredcites →https://doi.org/10.1007/3-540-45574-4_16openalex-snapshot
Compiler Techniques for Flat Neighborhood Networks
inferredcites →https://doi.org/10.1007/3-540-45937-5_14openalex-snapshot
StreamIt: A Language for Streaming Applications
inferredcites →https://doi.org/10.1007/3-540-58184-7_107openalex-snapshot
Static communications in parallel scientific programs
inferredcites →https://doi.org/10.1007/bfb0052218openalex-snapshot
Characterization of communication patterns in message-passing parallel scientific application programs
inferredcites →https://doi.org/10.1016/s0140-3664(00)00329-7openalex-snapshot
A high speed scheduler/controller for unbuffered banyan networks
inferredcites →https://doi.org/10.1109/2.335726openalex-snapshot
Communication styles for parallel systems
inferredcites →https://doi.org/10.1109/hpca.1995.386556openalex-snapshot
Toward high communication performance through compiled communications on a circuit switched interconnection network
inferredcites →https://doi.org/10.1109/hpca.2000.824347openalex-snapshot
Coherence communication prediction in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/hpca.2003.1183554openalex-snapshot
A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
inferredcites →https://doi.org/10.1109/isca.1992.753335openalex-snapshot
The Impact of Communication Locality on Large-Scale Multiprocessor Performance
inferredcites →https://doi.org/10.1109/pact.2000.888329openalex-snapshot
ASOC: a scalable, single-chip communications architecture
inferredcites →https://doi.org/10.1109/tpds.2003.1178875openalex-snapshot
Algorithms for supporting compiled communication
inferredcites →https://doi.org/10.1145/139669.140403openalex-snapshot
The impact of communication locality on large-scale multiprocessor performance
inferredcites →https://doi.org/10.1145/369028.369047openalex-snapshot
Compiler-directed shared-memory communication for iterative parallel applications
inferredcites →https://doi.org/10.5555/224659.224704openalex-snapshot
Analysis of communications and overhead reduction in multithreaded execution
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.jpdc.2008.07.008openalex-snapshot
A two-stage hardware scheduler combining greedy and optimal scheduling
inferred← citeshttps://doi.org/10.1109/hoti.2013.13openalex-snapshot
Deterministic Multiplexing of NoC on Grid CMPs
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639322openalex-snapshot
A compiler-based communication analysis approach for multiprocessor systems
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370470openalex-snapshot
Linking Compilation and Visualization for Massively Parallel Programs
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536344openalex-snapshot
Symbolic expression analysis for compiled communication
inferred← citeshttps://doi.org/10.1109/iwia.2007.8openalex-snapshot
Impact of Predictive Switching in 2-D Torus Networks
inferred← citeshttps://doi.org/10.1109/iwias.2006.33openalex-snapshot
Predictive Switching in 2-D Torus Routers
inferred← citeshttps://doi.org/10.1109/l-ca.2008.9openalex-snapshot
Transaction-Aware Network-on-Chip Resource Reservation
inferred← citeshttps://doi.org/10.1109/nocs.2009.5071468openalex-snapshot
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
inferred← citeshttps://doi.org/10.1109/sc.2005.48openalex-snapshot
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems
inferred← citeshttps://doi.org/10.1109/sc.2006.3openalex-snapshot
A Near-optimal Real-time Hardware Scheduler for Large Cardinality Crossbar Switches
inferred← citeshttps://doi.org/10.1109/tc.2007.1004openalex-snapshot
Low Diameter Interconnections for Routing in High-Performance Parallel Systems
inferred← citeshttps://doi.org/10.1109/tcad.2010.2048402openalex-snapshot
Virtual Point-to-Point Connections for NoCs
inferred← citeshttps://doi.org/10.1109/tnet.2013.2270436openalex-snapshot
Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches
inferred← citeshttps://doi.org/10.1109/tpds.2008.82openalex-snapshot
Compiler Techniques for Efficient Communications in Circuit Switched Networks for Multiprocessor Systems
inferred← citeshttps://doi.org/10.1109/tpds.2011.49openalex-snapshot
Efficiently Acquiring Communication Traces for Large-Scale Parallel Applications
inferred← citeshttps://doi.org/10.1109/tpds.2020.3011121openalex-snapshot
PredCom: A Predictive Approach to Collecting Approximated Communication Traces
inferred← citeshttps://doi.org/10.1142/s0129626408003570openalex-snapshot
SYMBOLIC EXPRESSION ANALYSIS FOR COMPILED COMMUNICATION
inferred← citeshttps://doi.org/10.1145/1188455.1188554openalex-snapshot
Interconnect routing and scheduling---A near-optimal real-time hardware scheduler for large cardinality crossbar switches
inferred← citeshttps://doi.org/10.1145/1477942.1477957openalex-snapshot
Packet prediction for speculative cut-through switching
inferred← citeshttps://doi.org/10.48456/tr-786openalex-snapshot
Communication flows in power-efficient Networks-on-Chips
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