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Power-performance efficiency of asymmetric multiprocessors for multi-threaded scientific applications
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.917539openalex-snapshot
Power: a first-class architectural design constraint
inferredcites →https://doi.org/10.1109/hpca.2005.25openalex-snapshot
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
inferredcites →https://doi.org/10.1109/ipdps.2005.251openalex-snapshot
Improvement of Power-Performance Efficiency for High-End Computing
inferredcites →https://doi.org/10.1109/ipdps.2005.390openalex-snapshot
Scheduling Algorithms for Effective Thread Pairing on Hybrid Multiprocessors
inferredcites →https://doi.org/10.1109/ipdps.2005.392openalex-snapshot
Scheduling Processor Voltage and Frequency in Server and Cluster Systems
inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot
Simultaneous multithreading: Maximizing on-chip parallelism
inferredcites →https://doi.org/10.1109/isca.2005.36openalex-snapshot
Mitigating Amdahls Law through EPI Throttling
inferredcites →https://doi.org/10.1109/isca.2005.51openalex-snapshot
The Impact of Performance Asymmetry in Emerging Multicore Architectures
inferredcites →https://doi.org/10.1109/isscc.2005.1493930openalex-snapshot
The design and implementation of a first-generation CELL processor
inferredcites →https://doi.org/10.1109/mc.2003.1250883openalex-snapshot
Dynamically tuning processor resources with adaptive processing
inferredcites →https://doi.org/10.1109/mc.2004.217openalex-snapshot
Power and energy management for server systems
inferredcites →https://doi.org/10.1109/mc.2005.379openalex-snapshot
Heterogeneous chip multiprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253185openalex-snapshot
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
inferredcites →https://doi.org/10.1109/sc.2005.3openalex-snapshot
A Power-Aware Run-Time System for High-Performance Computing
inferredcites →https://doi.org/10.1145/1006209.1006238openalex-snapshot
The energy efficiency of CMP vs. SMT for multimedia workloads
inferredcites →https://doi.org/10.1145/1048935.1050161openalex-snapshot
Improving the Scalability of Parallel Jobs by adding Parallel Awareness to the Operating System
inferredcites →https://doi.org/10.1145/1048935.1050204openalex-snapshot
The Case of the Missing Supercomputer Performance
inferredcites →https://doi.org/10.1145/1065944.1065967openalex-snapshot
Using multiple energy gears in MPI programs on a power-scalable cluster
inferredcites →https://doi.org/10.1145/1088149.1088190openalex-snapshot
System noise, OS clock ticks, and fine-grained parallel applications
inferredcites →https://doi.org/10.1145/381677.381702openalex-snapshot
Automatic performance setting for dynamic voltage scaling
inferredcites →https://doi.org/10.1145/781131.781137openalex-snapshot
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781118711897.ch20openalex-snapshot
Enabling Network Security in HPC Systems Using Heterogeneous CMPs
inferred← citeshttps://doi.org/10.1002/cpe.1454openalex-snapshot
Improving energy efficiency of asymmetric chip multithreaded multiprocessors through reduced OS noise scheduling
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.04.008openalex-snapshot
Cross-architecture prediction based scheduling for energy efficient execution on single-ISA heterogeneous chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/clustr.2007.4629224openalex-snapshot
A Feasibility Analysis of Power-Awareness and Energy Minimization in Modern Interconnects for High-Performance Computing
inferred← citeshttps://doi.org/10.1109/icwr.2017.7959321openalex-snapshot
Advanced adaptive probabilities and energy aware algorithm for scheduling tasks in MCC
inferred← citeshttps://doi.org/10.1109/igcc.2017.8323587openalex-snapshot
Evaluating energy and power profiling techniques for HPC workloads
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.91openalex-snapshot
Metrics for Evaluating Energy Saving Techniques for Resilient HPC Systems
inferred← citeshttps://doi.org/10.1109/iscc.2014.6912565openalex-snapshot
Green software development for multi-core architectures
inferred← citeshttps://doi.org/10.1109/isqed.2014.6783390openalex-snapshot
Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/itsim.2010.5561559openalex-snapshot
Power optimization in multi-processor systems
inferred← citeshttps://doi.org/10.1109/mm.2008.47openalex-snapshot
Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems
inferred← citeshttps://doi.org/10.1109/trustcom.2016.0222openalex-snapshot
Improving Energy Efficiency by Phase-Grained Migration for Asymmetric Multicore
inferred← citeshttps://doi.org/10.1177/1094342016665471openalex-snapshot
A survey on software methods to improve the energy efficiency of parallel computing
inferred← citeshttps://doi.org/10.31390/gradschool_dissertations.3918openalex-snapshot
Exploiting heterogeneity in Chip-Multiprocessor Design
inferred← citeshttps://doi.org/10.46670/jsst.2025.34.6.660openalex-snapshot
A Light-weight Asymmetric Multi-Processing FPGA Architecture for Real-time High-resolution LiDAR
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