On the public citation graph
Conditional Memory Ordering
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jpdc.1996.0136openalex-snapshot
Analyses and Optimizations for Shared Address Space Programs
inferredcites →https://doi.org/10.1007/978-3-540-24851-4_26openalex-snapshot
Lock Reservation for Java Reconsidered
inferredcites →https://doi.org/10.1007/bf02277859openalex-snapshot
Detecting causal relationships in distributed computations: In search of the holy grail
inferredcites →https://doi.org/10.1109/12.599898openalex-snapshot
How to make a correct multiprocess program execute correctly on a multiprocessor
inferredcites →https://doi.org/10.1109/2.485843openalex-snapshot
TreadMarks: shared memory computing on networks of workstations
inferredcites →https://doi.org/10.1109/cgo.2005.7openalex-snapshot
Automatically Reducing Repetitive Synchronization with a Just-in-Time Compiler for Java
inferredcites →https://doi.org/10.1109/isca.1990.134502openalex-snapshot
Weak ordering-a new definition
inferredcites →https://doi.org/10.1109/isca.1990.134503openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1992.753300openalex-snapshot
Lazy Release Consistency for Software Distributed Shared Memory
inferredcites →https://doi.org/10.1109/pact.2004.1342559openalex-snapshot
TO-lock: removing lock overhead using the owners' temporal locality
inferredcites →https://doi.org/10.1145/1065944.1065947openalex-snapshot
Compiler techniques for high performance sequentially consistent java programs
inferredcites →https://doi.org/10.1145/258492.258512openalex-snapshot
Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models
inferredcites →https://doi.org/10.1145/359545.359563openalex-snapshot
Time, clocks, and the ordering of events in a distributed system
inferredcites →https://doi.org/10.1145/378993.378997openalex-snapshot
Architecture and design of AlphaServer GS320
inferredcites →https://doi.org/10.1145/42190.42277openalex-snapshot
Efficient and correct execution of parallel programs that share memory
inferredcites →https://doi.org/10.1147/rd.494.0533openalex-snapshot
Operating system exploitation of the POWER5 system
inferredcites →https://doi.org/10.1184/r1/6607292openalex-snapshot
Midway : shared memory parallel programming with entry consistency for distributed memory multiprocessors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11817963_45openalex-snapshot
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
inferred← citeshttps://doi.org/10.1109/cgo.2009.30openalex-snapshot
Reducing Memory Ordering Overheads in Software Transactional Memory
inferred← citeshttps://doi.org/10.1109/imtc.2008.4547321openalex-snapshot
Aspect Oriented-based Software Synchronization in Automatic Measurement Systems
inferred← citeshttps://doi.org/10.1109/micro.2016.7783736openalex-snapshot
Racer: TSO consistency via race detection
inferred← citeshttps://doi.org/10.1109/tim.2010.2046602openalex-snapshot
A Petri Net-Based Software Synchronizer for Automatic Measurement Systems
inferred← citeshttps://doi.org/10.1109/tpds.2016.2633353openalex-snapshot
Fence-Free Synchronization with Dynamically Serialized Synchronization Variables
inferred← citeshttps://doi.org/10.1145/1250662.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1273440.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1555754.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/1555815.1555786openalex-snapshot
Decoupled store completion/silent deterministic replay
inferred← citeshttps://doi.org/10.1145/2786980openalex-snapshot
Leveraging Transactional Execution for Memory Consistency Model Emulation
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