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An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.142677openalex-snapshot
Virtual checkpoints: architecture and performance
inferredcites →https://doi.org/10.1109/71.80134openalex-snapshot
Error recovery in shared memory multiprocessors using private caches
inferredcites →https://doi.org/10.1109/dsn.2004.1311929openalex-snapshot
An architectural framework for providing reliability and security support
inferredcites →https://doi.org/10.1109/ftcs.1995.466961openalex-snapshot
Software rejuvenation: analysis, module and applications
inferredcites →https://doi.org/10.1109/ftcs.1995.466999openalex-snapshot
Checkpointing and its applications
inferredcites →https://doi.org/10.1109/iccd.2002.1106821openalex-snapshot
TAXI: Trace Analysis for x86 Interpretation
inferredcites →https://doi.org/10.1109/isca.2002.1003567openalex-snapshot
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.2002.1003568openalex-snapshot
SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery
inferredcites →https://doi.org/10.1109/micro.1999.809458openalex-snapshot
DIVA: a reliable substrate for deep submicron microarchitecture design
inferredcites →https://doi.org/10.1109/micro.2004.26openalex-snapshot
Minos: Control Data Attack Prevention Orthogonal to Memory Model
inferredcites →https://doi.org/10.1145/1024393.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/30350.30353openalex-snapshot
Checkpoint repair for out-of-order execution machines
inferredcites →https://doi.org/10.1145/70082.68191openalex-snapshot
Sheaved memory: architectural support for state saving and restoration in pages systems
inferredcites →https://doi.org/10.1145/859618.859631openalex-snapshot
Transient-fault recovery for chip multiprocessors
inferredcites →https://doi.org/10.3929/ethz-a-004287049openalex-snapshot
Performance evaluation of recent DRAM architectures for embedded systems
inferredcites →https://doi.org/10.48550/arxiv.cs/0406005openalex-snapshot
Microreboot -- A Technique for Cheap Recovery
inferredcites →https://doi.org/10.51983/ajcst-2019.8.s3.2112openalex-snapshot
The Methodology of N-Version Programming
inferredcites →https://doi.org/10.5555/563998.564027openalex-snapshot
Dual use of superscalar datapath for transient-fault detection and recovery
inferredcites →https://doi.org/10.7916/d86d6562openalex-snapshot
Building a Reactive Immune System for Software Services
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1145/1181309.1181319openalex-snapshot
Log-based architectures for general-purpose monitoring of deployed code
inferred← citeshttps://doi.org/10.1145/1346281.1346290openalex-snapshot
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1353534.1346290openalex-snapshot
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1353535.1346290openalex-snapshot
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1353536.1346290openalex-snapshot
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1378533.1378538openalex-snapshot
Parallelizing dynamic information flow tracking
inferred← citeshttps://doi.org/10.1145/1394608.1382153openalex-snapshot
Flexible Hardware Acceleration for Instruction-Grain Program Monitoring
inferred← citeshttps://doi.org/10.1145/2228360.2228435openalex-snapshot
Worst-case execution time analysis for parallel run-time monitoring
inferred← citeshttps://doi.org/10.1145/2487726.2487732openalex-snapshot
Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking
inferred← citeshttps://doi.org/10.1145/3460120.3484788openalex-snapshot
RealSWATT: Remote Software-based Attestation for Embedded Devices under Realtime Constraints
inferred← citeshttps://doi.org/10.15623/ijret.2013.0214016openalex-snapshot
ARCHITECTURE AND IMPLEMENTATION ISSUES OF MULTI-CORE PROCESSORS AND CACHING – A SURVEY
inferred← citeshttps://doi.org/10.17760/d20003253openalex-snapshot
Architectural support for software security
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