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Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC

https://doi.org/10.1109/ispdc.2010.23
0 signed · 23 inferred · view as graph

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-69384-0_47openalex-snapshot
Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications
inferredcites →https://doi.org/10.1109/40.621209openalex-snapshot
Simultaneous multithreading: a platform for next-generation processors
inferredcites →https://doi.org/10.1109/5.476078openalex-snapshot
The microarchitecture of superscalar processors
inferredcites →https://doi.org/10.1109/5.915377openalex-snapshot
Coming challenges in microarchitecture and architecture
inferredcites →https://doi.org/10.1109/parelec.2006.54openalex-snapshot
Multi-Core Processors: New Way to Achieve High System Performance
inferredcites →https://doi.org/10.1109/sc.2008.5222565openalex-snapshot
Scientific application-based performance comparison of SGI Altix 4700, IBM POWER5+, and SGI ICE 8200 supercomputers
inferredcites →https://doi.org/10.1142/s012962640800351xopenalex-snapshot
A PERFORMANCE EVALUATION OF THE NEHALEM QUAD-CORE PROCESSOR FOR SCIENTIFIC COMPUTING
inferredcites →https://doi.org/10.5555/1413370.1413378openalex-snapshot
Scientific application-based performance comparison of SGI Altix 4700, IBM POWER5+, and SGI ICE 8200 supercomputers

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.2948openalex-snapshot
High‐performance execution of service compositions: a multicore‐aware engine design
inferred← citeshttps://doi.org/10.1002/cpe.3191openalex-snapshot
Power usage of production supercomputers and production workloads
inferred← citeshttps://doi.org/10.1016/j.jocs.2013.04.002openalex-snapshot
Benchmarking JPEG 2000 implementations on modern CPU and GPU architectures
inferred← citeshttps://doi.org/10.1016/j.parco.2015.11.002openalex-snapshot
TracSim: Simulating and scheduling trapped power capacity to maximize machine room throughput
inferred← citeshttps://doi.org/10.1016/j.procs.2011.04.047openalex-snapshot
Early performance evaluation of AVX for HPC
inferred← citeshttps://doi.org/10.1016/j.procs.2012.04.208openalex-snapshot
Benchmarking Data and Compute Intensive Applications on Modern CPU and GPU Architectures
inferred← citeshttps://doi.org/10.1109/hpcsim.2014.6903787openalex-snapshot
Evaluation of Intel Xeon E5-2600v2 based cluster for technical computing workloads
inferred← citeshttps://doi.org/10.1109/ispdc.2011.13openalex-snapshot
The 2nd Generation Intel Core Processor. Architectural Features Supporting HPC
inferred← citeshttps://doi.org/10.1109/pdgc.2012.6449823openalex-snapshot
Performance evaluation of Intel Xeon E5-2600 family cluster using scientific and engineering benchmarks
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2019.8920389openalex-snapshot
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications
inferred← citeshttps://doi.org/10.1145/2744769.2744888openalex-snapshot
Parallel circuit simulation using the direct method on a heterogeneous cloud
inferred← citeshttps://doi.org/10.1155/2015/739107openalex-snapshot
Performance of a Code Migration for the Simulation of Supersonic Ejector Flow to SMP, MIC, and GPU Using OpenMP, OpenMP+LEO, and OpenACC Directives
inferred← citeshttps://doi.org/10.1504/ijhpcn.2016.076269openalex-snapshot
Direct-to-chip liquid cooling for reducing power consumption in a subarctic supercomputer centre
inferred← citeshttps://doi.org/10.1587/transele.e97.c.386openalex-snapshot
CoDMA: Buffer Avoided Data Exchange in Distributed Memory Systems
inferred← citeshttps://doi.org/10.2172/1082971openalex-snapshot
Parallelization and checkpointing of GPU applications through program transformation
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