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Optimal Parallel Hardware K-Sorter and Top K-Sorter, with FPGA Implementations
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1006/jpdc.1998.1462openalex-snapshot
A Randomized Parallel Sorting Algorithm with an Experimental Study
inferredcites →https://doi.org/10.1006/jpdc.2001.1808openalex-snapshot
Partitioned Parallel Radix Sort
inferredcites →https://doi.org/10.1016/j.jpdc.2008.05.012openalex-snapshot
Fast parallel GPU-sorting using a hybrid algorithm
inferredcites →https://doi.org/10.1023/a:1021734202931openalex-snapshot
Parallel Merge Sort with Load Balancing
inferredcites →https://doi.org/10.1093/ietisy/e88-d.7.1350openalex-snapshot
Hardware n Choose k Counters with Applications to the Partial Exhaustive Search
inferredcites →https://doi.org/10.1109/71.532111openalex-snapshot
Fast parallel sorting under LogP: experience with the CM-5
inferredcites →https://doi.org/10.1109/aspdac.2003.1195043openalex-snapshot
An image retrieval system using FPGAs
inferredcites →https://doi.org/10.1109/icecs.2009.5410898openalex-snapshot
Unbalanced FIFO sorting for FPGA-based systems
inferredcites →https://doi.org/10.1109/icpads.2008.71openalex-snapshot
Processor, Assembler, and Compiler Design Education Using an FPGA
inferredcites →https://doi.org/10.1109/ieeestd.2008.4610935openalex-snapshot
IEEE Standard for Floating-Point Arithmetic
inferredcites →https://doi.org/10.1109/ipdps.2012.30openalex-snapshot
A Novel Sorting Algorithm for Many-core Architectures Based on Adaptive Bitonic Sort
inferredcites →https://doi.org/10.1109/ipps.1997.580914openalex-snapshot
Optimizing parallel bitonic sort
inferredcites →https://doi.org/10.1109/sasp.2011.5941075openalex-snapshot
Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron Collider
inferredcites →https://doi.org/10.1142/s0129054111008568openalex-snapshot
AN EFFICIENT PARALLEL SORTING COMPATIBLE WITH THE STANDARD QSORT
inferredcites →https://doi.org/10.1145/1468075.1468121openalex-snapshot
Sorting networks and their applications
inferredcites →https://doi.org/10.1145/276304.276313openalex-snapshot
Efficiently mining long patterns from databases
inferredcites →https://doi.org/10.1145/277830.277903openalex-snapshot
Load balanced parallel radix sort
inferredcites →https://doi.org/10.1147/rd.225.0509openalex-snapshot
Algorithm and Hardware for a Merge Sort Using Multiple Processors
inferredcites →https://doi.org/10.13182/nse70-a19705openalex-snapshot
The Art of Computer Programming
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/candar.2016.0023openalex-snapshot
A Cost-Effective and Scalable Merge Sorter Tree on FPGAs
inferred← citeshttps://doi.org/10.1109/candar.2016.0103openalex-snapshot
A Hardware Sorter for Almost Sorted Sequences, with FPGA Implementations
inferred← citeshttps://doi.org/10.1109/icosec61587.2024.10722670openalex-snapshot
K-degree Comparison-free Parallel Sorter with Duplicate Element Handler
inferred← citeshttps://doi.org/10.1109/icrito.2017.8342427openalex-snapshot
Iterative parallel shift sort : Optimization and design for area constrained applications
inferred← citeshttps://doi.org/10.1109/ipdpsw.2019.00112openalex-snapshot
FIFO-Based Hardware Sorters for High Bandwidth Memory
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00110openalex-snapshot
A Comparison-free Hardware Sorting Engine
inferred← citeshttps://doi.org/10.1109/mwscas57524.2023.10406121openalex-snapshot
An Energy Efficient Sorting Architecture with Cell-Gating for Top-K Sorting on FPGA
inferred← citeshttps://doi.org/10.1109/tcad.2021.3131554openalex-snapshot
Worst Case O(N) Comparison-Free Hardware Sorting Engine
inferred← citeshttps://doi.org/10.1109/tcad.2022.3207689openalex-snapshot
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting
inferred← citeshttps://doi.org/10.1109/tcad.2024.3446857openalex-snapshot
NICE: A Nonintrusive In-Storage-Computing Framework for Embedded Applications
inferred← citeshttps://doi.org/10.1109/tcsii.2019.2938892openalex-snapshot
A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA
inferred← citeshttps://doi.org/10.1109/tcsii.2021.3058245openalex-snapshot
A Novel Scheme for Real-Time Max/Min-Set-Selection Sorters on FPGA
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3613706openalex-snapshot
FPGA Implementation of Sparsity Adaptive Atomic Correlation Difference Pursuit Algorithm for Compressed Sensing
inferred← citeshttps://doi.org/10.1587/elex.15.20171272openalex-snapshot
Design of memory efficient FIFO-based merge sorter
inferred← citeshttps://doi.org/10.1587/transfun.2019eal2133openalex-snapshot
Sorting Matrix Architecture for Continuous Data Sequences
inferred← citeshttps://doi.org/10.1587/transfun.2021eal2103openalex-snapshot
Resource Efficient Top-K Sorter on FPGA
inferred← citeshttps://doi.org/10.1587/transfun.e100.a.1074openalex-snapshot
Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy
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