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Analytical Model for the Propagation Delay of Through Silicon Vias

https://doi.org/10.1109/isqed.2008.4479795
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/0016-0032(52)90438-9openalex-snapshot
Dimensional analysis and theory of models
inferredcites →https://doi.org/10.1016/b978-0-12-370620-1.x5000-xopenalex-snapshot
Applied Dimensional Analysis and Modeling
inferredcites →https://doi.org/10.1109/22.297805openalex-snapshot
Capacitance computations in a multilayered dielectric medium using closed-form spatial Green's functions
inferredcites →https://doi.org/10.1109/5.929647openalex-snapshot
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
inferredcites →https://doi.org/10.1109/92.831439openalex-snapshot
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
inferredcites →https://doi.org/10.1109/92.902261openalex-snapshot
System-level performance evaluation of three-dimensional integrated circuits
inferredcites →https://doi.org/10.1109/epep.2005.1563724openalex-snapshot
High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package
inferredcites →https://doi.org/10.1109/iccd.2004.1347939openalex-snapshot
3D processing technology and its impact on iA32 microprocessors
inferredcites →https://doi.org/10.1109/iitc.2002.1014915openalex-snapshot
Opportunities for reduced power dissipation using three-dimensional integration
inferredcites →https://doi.org/10.1109/iscas.2001.922261openalex-snapshot
Power trends and performance characterization of 3-dimensional integration
inferredcites →https://doi.org/10.1109/jssc.1983.1051966openalex-snapshot
Approximation of wiring delay in MOSFET LSI
inferredcites →https://doi.org/10.1109/tmtt.2005.852782openalex-snapshot
Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates
inferredcites →https://doi.org/10.1109/wmed.2004.1297363openalex-snapshot
Electrical characterization of through-wafer interconnects
inferredcites →https://doi.org/10.1139/cjce-25-4-802openalex-snapshot
Applied dimensional analysis and modeling

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Estimation Of Attenuation And Phase Delay In Driving Voltage Waveform Of An Ultra-High-Speed Image Sensor By Dimensional Analysis
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Estimation Of Attenuation And Phase Delay In Driving Voltage Waveform Of A Digital-Noiseless, Ultra-High-Speed Image Sensor
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OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture
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3D/TSV-Enabling Technologies
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Exploring a Design Space of 3-D Stacked Vector Processors
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TSV- and delay-aware 3D-IC floorplanning
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An analysis of the eddy effect in through-silicon vias based on Cu and CNT bundles: the impact on crosstalk and power
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2020.106592openalex-snapshot
Power and performance analysis of 3D network-on-chip architectures
inferred← citeshttps://doi.org/10.1016/j.mejo.2009.10.006openalex-snapshot
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
inferred← citeshttps://doi.org/10.1016/j.simpat.2019.101929openalex-snapshot
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures
inferred← citeshttps://doi.org/10.1080/03772063.2021.1982410openalex-snapshot
Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via
inferred← citeshttps://doi.org/10.1109/3dic.2009.5306541openalex-snapshot
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
inferred← citeshttps://doi.org/10.1109/3dic.2009.5306566openalex-snapshot
Evaluation of fine grain 3-D integrated arithmetic units
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Developing digital test sequences for through-silicon vias within 3D structures
inferred← citeshttps://doi.org/10.1109/3dic.2013.6702358openalex-snapshot
TSV capacitance aware 3-D floorplanning
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Vertically integrated processor and memory module design for vector supercomputers
inferred← citeshttps://doi.org/10.1109/aspdac.2011.5722180openalex-snapshot
Equivalent lumped element models for various n-port Through Silicon Vias networks
inferred← citeshttps://doi.org/10.1109/eptc.2008.4763434openalex-snapshot
Design and Analysis of an I-shaped TSV Structure for 3D SiP
inferred← citeshttps://doi.org/10.1109/icacci.2018.8554639openalex-snapshot
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)
inferred← citeshttps://doi.org/10.1109/icecs.2012.6463532openalex-snapshot
Modeling and analysis of through silicon via: Electromagnetic and device simulation approach
inferred← citeshttps://doi.org/10.1109/icept-hdp.2012.6474583openalex-snapshot
Simulation-based investigation in effects of design parameters on electrical characters for a TSV-bump combination
inferred← citeshttps://doi.org/10.1109/icept.2014.6922776openalex-snapshot
Simulation study of a novel TSV structure
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Delay and power optimization with TSV-aware 3D floorplanning
inferred← citeshttps://doi.org/10.1109/isqed.2017.7918314openalex-snapshot
STA compatible backend design flow for TSV-based 3-D ICs
inferred← citeshttps://doi.org/10.1109/socc.2014.6948921openalex-snapshot
Comparison between optimal interconnection network in different 2D and 3D NoC structures
inferred← citeshttps://doi.org/10.1109/tcad.2012.2203598openalex-snapshot
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates
inferred← citeshttps://doi.org/10.1109/tcpmt.2010.2101910openalex-snapshot
Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling
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Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects
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High-Frequency Modeling of TSVs for 3-D Chip Integration and Silicon Interposers Considering Skin-Effect, Dielectric Quasi-TEM and Slow-Wave Modes
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3-D Power Delivery Network’s Subblocks and Regulator Placement Optimized by Evolutionary Algorithm
inferred← citeshttps://doi.org/10.1109/ted.2009.2026200openalex-snapshot
Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance
inferred← citeshttps://doi.org/10.1109/ted.2010.2076382openalex-snapshot
Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs
inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2011910openalex-snapshot
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration
inferred← citeshttps://doi.org/10.1109/tvlsi.2010.2090049openalex-snapshot
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
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A high sensitivity and process tolerant digital thermal sensing scheme for 3-D Ics
inferred← citeshttps://doi.org/10.1145/2633948.2633955openalex-snapshot
Compact Models and Model Standard for 2.5D and 3D Integration
inferred← citeshttps://doi.org/10.12677/ojcs.2020.93008openalex-snapshot
Study on Extracting Analytical Formula for TSV Resistance Parameter Calculation in 3D IC
inferred← citeshttps://doi.org/10.15760/etd.3404openalex-snapshot
Early Layout Design Exploration in TSV-based 3D Integrated Circuits
inferred← citeshttps://doi.org/10.15760/etd.5509openalex-snapshot
Early Layout Design Exploration in TSV-based 3D Integrated Circuits
inferred← citeshttps://doi.org/10.15760/etd.7437openalex-snapshot
Dynamic Through-Silicon Via Clustering in 3D IC Floorplanning for Early Performance Optimization
inferred← citeshttps://doi.org/10.5104/jiepeng.4.119openalex-snapshot
Propagation Delay Analysis of a Soft Open Defect inside a TSV
inferred← citeshttps://doi.org/10.5555/1950815.1950862openalex-snapshot
Equivalent lumped element models for various n-port through silicon vias networks
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