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Ending Piracy of Integrated Circuits
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/9781119644682openalex-snapshot
Security Engineering: A Guide to Building Dependable Distributed Systems
inferredcites →https://doi.org/10.1007/0-387-31005-3openalex-snapshot
Logic Synthesis and Verification Algorithms
inferredcites →https://doi.org/10.1007/3-540-45496-9_7openalex-snapshot
Intellectual Property Metering
inferredcites →https://doi.org/10.1007/b117060openalex-snapshot
Logic Synthesis and Verification Algorithms
inferredcites →https://doi.org/10.1109/81.586025openalex-snapshot
An integrated analog/digital random noise source
inferredcites →https://doi.org/10.1109/hst.2008.4559052openalex-snapshot
Extended abstract: Circuit CAD tools as a security threat
inferredcites →https://doi.org/10.1109/hst.2009.5224964openalex-snapshot
Analysis and design of active IC metering schemes
inferredcites →https://doi.org/10.1109/isscc.2007.373465openalex-snapshot
True Random Number Generator with a Metastability-Based Quality Control
inferredcites →https://doi.org/10.1109/isscc.2007.373466openalex-snapshot
A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations
inferredcites →https://doi.org/10.1109/isscc.2007.373611openalex-snapshot
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
inferredcites →https://doi.org/10.1109/jssc.2007.910961openalex-snapshot
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations
inferredcites →https://doi.org/10.1109/jssc.2007.910965openalex-snapshot
True Random Number Generator With a Metastability-Based Quality Control
inferredcites →https://doi.org/10.1109/mspec.2007.4283527openalex-snapshot
Plans for Next-Gen Chips Imperiled
inferredcites →https://doi.org/10.1109/tvlsi.2005.859470openalex-snapshot
Extracting secret keys from integrated circuits
inferredcites →https://doi.org/10.1145/1278480.1278484openalex-snapshot
Physical unclonable functions for device authentication and secret key generation
inferredcites →https://doi.org/10.5555/1326073.1326215openalex-snapshot
Remote activation of ICs for piracy prevention and digital right management
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.7058openalex-snapshot
Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications
inferred← citeshttps://doi.org/10.1002/spy2.233openalex-snapshot
Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT
inferred← citeshttps://doi.org/10.1007/978-1-4419-8080-9_5openalex-snapshot
Hardware Metering: A Survey
inferred← citeshttps://doi.org/10.1007/978-3-030-15334-2_1openalex-snapshot
The Need for Logic Locking
inferred← citeshttps://doi.org/10.1007/978-3-030-15334-2_2openalex-snapshot
A Brief History of Logic Locking
inferred← citeshttps://doi.org/10.1007/978-3-030-41025-4_12openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-43605-6_8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-47218-4_4openalex-snapshot
Hardware Trojans in Microcircuits
inferred← citeshttps://doi.org/10.1007/978-3-030-47218-4_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-64448-2_16openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-71522-9_1655openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-78841-4_6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-030-79701-0_4openalex-snapshot
Introduction to Hardware Security for FPGA Based Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-15699-1_7openalex-snapshot
Hardware Security of SFQ Circuits
inferred← citeshttps://doi.org/10.1007/978-3-031-16344-9_3openalex-snapshot
Flash: A “Forgotten” Technology in VLSI Design
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_1openalex-snapshot
Introduction to CAD for Hardware Security
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_11openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-031-54400-2_5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-14971-4_2openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-50057-7_8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_10openalex-snapshot
Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks
inferred← citeshttps://doi.org/10.1007/978-3-319-68511-3_2openalex-snapshot
Introduction to Hardware Trojans
inferred← citeshttps://doi.org/10.1007/978-3-319-93100-5_20openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-27739-9_1655-1openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-642-40349-1_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-981-13-5950-7_16openalex-snapshot
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks
inferred← citeshttps://doi.org/10.1007/978-981-15-7527-3_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-981-19-0542-1_3openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10836-019-05800-4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10836-022-06028-5openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10836-023-06061-yopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10836-025-06171-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11277-024-11334-6openalex-snapshot
Hardware Trojans Detection and Prevention Techniques Review
inferred← citeshttps://doi.org/10.1007/s11390-014-1479-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s13389-022-00294-xopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s13389-024-00350-8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s41635-018-0033-6openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s41635-018-0036-3openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s41635-018-0044-3openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s41635-019-00080-yopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s41635-026-00177-1openalex-snapshot
TroLLoc: Security Closure against Hardware Trojans by Logic Locking and Layout Hardening
inferred← citeshttps://doi.org/10.1007/s42979-022-01194-xopenalex-snapshot
Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00011-3openalex-snapshot
Electronics Supply Chain
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00018-6openalex-snapshot
Security and Trust Assessment, and Design for Security
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00019-8openalex-snapshot
Hardware Obfuscation
inferred← citeshttps://doi.org/10.1016/j.comnet.2020.107593openalex-snapshot
A survey on physical unclonable function (PUF)-based security solutions for Internet of Things
inferred← citeshttps://doi.org/10.1016/j.eswa.2022.118298openalex-snapshot
ObfSec: Measuring the security of obfuscations from a testing perspective
inferred← citeshttps://doi.org/10.1016/j.hcc.2023.100114openalex-snapshot
A survey on security analysis of machine learning-oriented hardware and software intellectual property
inferred← citeshttps://doi.org/10.1016/j.mejo.2019.06.006openalex-snapshot
Design of anti-key leakage camouflage gate circuit for reverse engineering based on dummy vias
inferred← citeshttps://doi.org/10.1016/j.protcy.2013.12.373openalex-snapshot
Updation of Activation Sequence of a Chip after its Deployment for Access Control
inferred← citeshttps://doi.org/10.1016/j.sse.2022.108381openalex-snapshot
Reconfigurable field effect transistors: A technology enablers perspective
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.02.006openalex-snapshot
Survey on recent counterfeit IC detection techniques and future research directions
inferred← citeshttps://doi.org/10.1016/j.vlsi.2020.05.001openalex-snapshot
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack
inferred← citeshttps://doi.org/10.1016/j.vlsi.2026.102677openalex-snapshot
Ring oscillator-based on-chip aging sensor for recycled IC detection
inferred← citeshttps://doi.org/10.1021/acsanm.2c02807openalex-snapshot
Logic Locking of Integrated Circuits Enabled by Nanoscale MoS2-Based Memtransistors
inferred← citeshttps://doi.org/10.1038/s41928-018-0146-5openalex-snapshot
A provable key destruction scheme based on memristive crossbar arrays
inferred← citeshttps://doi.org/10.1049/cds2.12080openalex-snapshot
TVD‐PB logic circuit based on camouflaging circuit for IoT security
inferred← citeshttps://doi.org/10.1049/iet-cdt.2014.0028openalex-snapshot
Survey of hardware protection of design data for integrated circuits and intellectual properties
inferred← citeshttps://doi.org/10.1109/access.2020.3040395openalex-snapshot
Dynamic Game for Strategy Selection in Hardware Trojan Attack and Defense
inferred← citeshttps://doi.org/10.1109/access.2023.3332543openalex-snapshot
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption
inferred← citeshttps://doi.org/10.1109/acsac63791.2024.00066openalex-snapshot
FLUENT: A Tool for Efficient Mixed-Protocol Semi-Private Function Evaluation
inferred← citeshttps://doi.org/10.1109/apccas62602.2024.10808726openalex-snapshot
Toward Structurally Safe Design-for-Trust Techniques
inferred← citeshttps://doi.org/10.1109/asianhost56390.2022.10022175openalex-snapshot
On the Limitations of Logic Locking the Approximate Circuits
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473877openalex-snapshot
LOOPLock 3.0: A Robust Cyclic Logic Locking Approach
inferred← citeshttps://doi.org/10.1109/ats.2016.24openalex-snapshot
On Test Points Enhancing Hardware Security
inferred← citeshttps://doi.org/10.1109/ats.2017.20openalex-snapshot
A New Active IC Metering Technique Based on Locking Scan Cells
inferred← citeshttps://doi.org/10.1109/dac.2018.8465830openalex-snapshot
TAO: Techniques for Algorithm-Level Obfuscation during High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586314openalex-snapshot
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247822openalex-snapshot
SimLL: Similarity-Based Logic Locking Against Machine Learning Attacks
inferred← citeshttps://doi.org/10.1109/dft52944.2021.9568356openalex-snapshot
GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains
inferred← citeshttps://doi.org/10.1109/dft56152.2022.9962349openalex-snapshot
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
inferred← citeshttps://doi.org/10.1109/dsd57027.2022.00073openalex-snapshot
Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis
inferred← citeshttps://doi.org/10.1109/ectc51906.2022.00366openalex-snapshot
Security challenges of MEMS devices in HI packaging
inferred← citeshttps://doi.org/10.1109/ets.2019.8791550openalex-snapshot
Revisiting Logic Locking for Reversible Computing
inferred← citeshttps://doi.org/10.1109/globecom59602.2025.11432758openalex-snapshot
Anti-Counterfeiting Design of Bluetooth Transceivers Through Logic Locking
inferred← citeshttps://doi.org/10.1109/host45689.2020.9300258openalex-snapshot
The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes
inferred← citeshttps://doi.org/10.1109/host49136.2021.9702267openalex-snapshot
Fun-SAT: Functional Corruptibility-Guided SAT-Based Attack on Sequential Logic Encryption
inferred← citeshttps://doi.org/10.1109/host54066.2022.9840239openalex-snapshot
Secuirty Metrics for Logic Circuits
inferred← citeshttps://doi.org/10.1109/host54066.2022.9840282openalex-snapshot
pHGen: A pH-Based Key Generation Mechanism Using ISFETs
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133696openalex-snapshot
LEDA: Locking Enabled Differential Analysis of Cryptographic Circuits
inferred← citeshttps://doi.org/10.1109/hst.2009.5224964openalex-snapshot
Analysis and design of active IC metering schemes
inferred← citeshttps://doi.org/10.1109/icacci.2018.8554562openalex-snapshot
Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Hardware Obfuscation Approach at RTL Level
inferred← citeshttps://doi.org/10.1109/icaita67588.2025.11137873openalex-snapshot
Q-Learning-Based Obfuscation Finite State Machine for Hardware IP Protection
inferred← citeshttps://doi.org/10.1109/iccad.2013.6691207openalex-snapshot
Hardware security: Threat models and metrics
inferred← citeshttps://doi.org/10.1109/iccad.2014.7001347openalex-snapshot
BIST-PUF: Online, hardware-based evaluation of physically unclonable circuit identifiers
inferred← citeshttps://doi.org/10.1109/iccad.2014.7001361openalex-snapshot
Protecting integrated circuits from piracy with test-aware logic locking
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203758openalex-snapshot
Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging
inferred← citeshttps://doi.org/10.1109/iccad.2017.8329993openalex-snapshot
Front-end-of-line attacks in split manufacturing
inferred← citeshttps://doi.org/10.1109/iccad45719.2019.8942047openalex-snapshot
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
inferred← citeshttps://doi.org/10.1109/iccad45719.2019.8942100openalex-snapshot
Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality
inferred← citeshttps://doi.org/10.1109/iccad45719.2019.8942150openalex-snapshot
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643476openalex-snapshot
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240725openalex-snapshot
Invited Paper: Circuit and Architecture Design with Emerging Computing Paradigms
inferred← citeshttps://doi.org/10.1109/icccit62592.2025.10927961openalex-snapshot
Enhancing Security in Logic-Locked Systems Through UART-Based Key Authentication
inferred← citeshttps://doi.org/10.1109/iccd.2018.00075openalex-snapshot
How Multi-Threshold Designs Can Protect Analog IPs
inferred← citeshttps://doi.org/10.1109/icce-taiwan66881.2025.11207881openalex-snapshot
A Machine Learning-Based Approach to Attacking Obfuscated Finite State Machines
inferred← citeshttps://doi.org/10.1109/icces54183.2022.9835923openalex-snapshot
Preventive Measure of SAT Attack by Integrating Anti-SAT on Locked Circuit for Improving Hardware Security
inferred← citeshttps://doi.org/10.1109/icdcs54290.2022.9780725openalex-snapshot
Review on Logic Locking Attacks in Hardware Security
inferred← citeshttps://doi.org/10.1109/iceca.2019.8821880openalex-snapshot
Weighted Logic Locking to Increase Hamming Distance against Key Sensitization Attack
inferred← citeshttps://doi.org/10.1109/icee50131.2020.9260694openalex-snapshot
Logic Encryption to Prevent Trojan Insertion with Dual-Function Gates
inferred← citeshttps://doi.org/10.1109/iciiet55458.2022.9967523openalex-snapshot
A Novel Logic Locking Technique with Observability Measures to Thwart Hardware Trojans
inferred← citeshttps://doi.org/10.1109/iemcon53756.2021.9623118openalex-snapshot
Developing Attack Resilience in Y86 Processor using Logic Locking
inferred← citeshttps://doi.org/10.1109/iementech48150.2019.8981198openalex-snapshot
Logic Encryption of Combinational Circuits
inferred← citeshttps://doi.org/10.1109/igsc51522.2020.9290857openalex-snapshot
Normally-off computing design methodology using spintronics: from device to architectures
inferred← citeshttps://doi.org/10.1109/indicon45594.2018.8987098openalex-snapshot
Design and Analysis of Logic Encryption Based 128-Bit AES Algorithm: A Case Study
inferred← citeshttps://doi.org/10.1109/iolts.2017.8046226openalex-snapshot
Weighted logic locking: A new approach for IC piracy protection
inferred← citeshttps://doi.org/10.1109/iolts.2018.8474189openalex-snapshot
Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes
inferred← citeshttps://doi.org/10.1109/iolts.2019.8854466openalex-snapshot
An Efficient SAT-Attack Algorithm Against Logic Encryption
inferred← citeshttps://doi.org/10.1109/iolts52814.2021.9486716openalex-snapshot
Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron
inferred← citeshttps://doi.org/10.1109/iscas.2017.8050605openalex-snapshot
Hardware-based anti-counterfeiting techniques for safeguarding supply chain integrity
inferred← citeshttps://doi.org/10.1109/iscas.2017.8050883openalex-snapshot
An overview of hardware intellectual property protection
inferred← citeshttps://doi.org/10.1109/iscas.2019.8702683openalex-snapshot
Increasing the SAT Attack Resiliency of In-Cone Logic Locking
inferred← citeshttps://doi.org/10.1109/iscas.2019.8702704openalex-snapshot
Functional Reverse Engineering on SAT-Attack Resilient Logic Locking
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180687openalex-snapshot
S4oC: A Self-Optimizing, Self-Adapting Secure System-on-Chip Design Framework to Tackle Unknown Threats — A Network Theoretic, Learning Approach
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180707openalex-snapshot
Reducing Logic Locking Key Leakage through the Scan Chain
inferred← citeshttps://doi.org/10.1109/iscas46773.2023.10182222openalex-snapshot
DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking
inferred← citeshttps://doi.org/10.1109/ised.2018.8704003openalex-snapshot
A Novel Logical Locking Technique Against Key-Guessing Attacks
inferred← citeshttps://doi.org/10.1109/ises52644.2021.00078openalex-snapshot
A Holistic Blockchain Based IC Traceability Technique
inferred← citeshttps://doi.org/10.1109/ises52644.2021.00095openalex-snapshot
SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme
inferred← citeshttps://doi.org/10.1109/isqed48828.2020.9137044openalex-snapshot
How to Retrieve PUF Response from a Fabricated Chip Securely?
inferred← citeshttps://doi.org/10.1109/isqed48828.2020.9137052openalex-snapshot
SATConda: SAT to SAT-Hard Clause Translator
inferred← citeshttps://doi.org/10.1109/isqed51717.2021.9424321openalex-snapshot
ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing
inferred← citeshttps://doi.org/10.1109/isqed54688.2022.9806219openalex-snapshot
Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528687openalex-snapshot
DECOR: Enhancing Logic Locking Against Machine Learning-Based Attacks
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014341openalex-snapshot
REDACTOR: eFPGA Redaction for DNN Accelerator Security
inferred← citeshttps://doi.org/10.1109/isvlsi.2017.26openalex-snapshot
Centrality Indicators for Efficient and Scalable Logic Masking
inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00119openalex-snapshot
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00068openalex-snapshot
Deep State Encryption for Sequential Logic Circuits
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00037openalex-snapshot
SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption
inferred← citeshttps://doi.org/10.1109/isvlsi61997.2024.00073openalex-snapshot
Attacking Multi-Tenant FPGAs Without Manual Placement and Routing
inferred← citeshttps://doi.org/10.1109/itc-asia.2019.00030openalex-snapshot
Characterization of Locked Sequential Circuits via ATPG
inferred← citeshttps://doi.org/10.1109/itc44170.2019.9000113openalex-snapshot
Breaking Analog Locking Techniques via Satisfiability Modulo Theories
inferred← citeshttps://doi.org/10.1109/itc44170.2019.9000130openalex-snapshot
Characterization of Locked Combinational Circuits via ATPG
inferred← citeshttps://doi.org/10.1109/itc44170.2019.9000167openalex-snapshot
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
inferred← citeshttps://doi.org/10.1109/itc44778.2020.9325209openalex-snapshot
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits
inferred← citeshttps://doi.org/10.1109/itc50571.2021.00030openalex-snapshot
Characterizing Corruptibility of Logic Locks using ATPG
inferred← citeshttps://doi.org/10.1109/iwssip55020.2022.9854421openalex-snapshot
Experimental setup for Hardware Encryption logic evaluation for e-learning
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3084400openalex-snapshot
Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security
inferred← citeshttps://doi.org/10.1109/jproc.2014.2335155openalex-snapshot
A Primer on Hardware Security: Models, Methods, and Metrics
inferred← citeshttps://doi.org/10.1109/jssc.2021.3112182openalex-snapshot
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device
inferred← citeshttps://doi.org/10.1109/latw.2015.7102410openalex-snapshot
Improving logic obfuscation via logic cone analysis
inferred← citeshttps://doi.org/10.1109/les.2021.3127682openalex-snapshot
SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage
inferred← citeshttps://doi.org/10.1109/mdat.2020.2984224openalex-snapshot
Hardware Obfuscation and Logic Locking: A Tutorial Introduction
inferred← citeshttps://doi.org/10.1109/mdt.2010.24openalex-snapshot
Preventing IC Piracy Using Reconfigurable Logic Barriers
inferred← citeshttps://doi.org/10.1109/mtv.2018.00014openalex-snapshot
A Perceptron-Inspired Technique for Hardware Obfuscation
inferred← citeshttps://doi.org/10.1109/mwscas.2014.6908424openalex-snapshot
Can the SHIELD protect our integrated circuits?
inferred← citeshttps://doi.org/10.1109/mwscas48704.2020.9184664openalex-snapshot
SLED: Sequential Logic Encryption Using Dynamic Keys
inferred← citeshttps://doi.org/10.1109/mwscas57524.2023.10405970openalex-snapshot
Hybrid Shielding: Amplifying the Power of Camouflaging and Logic Encryption
inferred← citeshttps://doi.org/10.1109/newcas57931.2023.10198196openalex-snapshot
Formal Analysis of Camouflaged Reconfigurable Circuits
inferred← citeshttps://doi.org/10.1109/nss/mic44845.2022.10399045openalex-snapshot
Design of Hardware Security Architecture and IP Protection Circuits of a Mixed-Signal Front-End Readout ASIC for Radiation Detectors
inferred← citeshttps://doi.org/10.1109/paine49178.2020.9337734openalex-snapshot
ATPG-Guided Fault Injection Attacks on Logic Locking
inferred← citeshttps://doi.org/10.1109/paine58317.2023.10317962openalex-snapshot
PLaNe: Reverse Engineering of Planar Layouts to Gate-Level Netlists
inferred← citeshttps://doi.org/10.1109/secdev.2019.00020openalex-snapshot
System-Level Framework for Logic Obfuscation with Quantified Metrics for Evaluation
inferred← citeshttps://doi.org/10.1109/smacd.2019.8795279openalex-snapshot
Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application
inferred← citeshttps://doi.org/10.1109/smarttechcon.2017.8358398openalex-snapshot
Fast and secure random number generation using low-cost EEG and pseudo random number generator
inferred← citeshttps://doi.org/10.1109/socc46988.2019.1570547988openalex-snapshot
A Glitch Key-Gate for Logic Locking
inferred← citeshttps://doi.org/10.1109/socc52499.2021.9739619openalex-snapshot
Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core
inferred← citeshttps://doi.org/10.1109/tasc.2021.3065301openalex-snapshot
Logic Locking in Single Flux Quantum Circuits
inferred← citeshttps://doi.org/10.1109/tasc.2022.3151881openalex-snapshot
Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures
inferred← citeshttps://doi.org/10.1109/tc.2013.193openalex-snapshot
Fault Analysis-Based Logic Encryption
inferred← citeshttps://doi.org/10.1109/tc.2016.2576444openalex-snapshot
Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection
inferred← citeshttps://doi.org/10.1109/tcad.2015.2404876openalex-snapshot
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2015.2428707openalex-snapshot
Belling the CAD: Toward Security-Centric Electronic System Design
inferred← citeshttps://doi.org/10.1109/tcad.2015.2459038openalex-snapshot
Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules
inferred← citeshttps://doi.org/10.1109/tcad.2015.2474373openalex-snapshot
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2015.2511144openalex-snapshot
On Improving the Security of Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2018.2801240openalex-snapshot
Hardware Protection via Logic Locking Test Points
inferred← citeshttps://doi.org/10.1109/tcad.2019.2897699openalex-snapshot
Logic Locking With Provable Security Against Power Analysis Attacks
inferred← citeshttps://doi.org/10.1109/tcad.2019.2917856openalex-snapshot
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime
inferred← citeshttps://doi.org/10.1109/tcad.2019.2925387openalex-snapshot
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
inferred← citeshttps://doi.org/10.1109/tcad.2019.2944586openalex-snapshot
Keynote: A Disquisition on Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2019.2960351openalex-snapshot
LOOPLock: Logic Optimization-Based Cyclic Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2020.2968898openalex-snapshot
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
inferred← citeshttps://doi.org/10.1109/tcad.2020.2981034openalex-snapshot
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
inferred← citeshttps://doi.org/10.1109/tcad.2020.3029133openalex-snapshot
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2021.3053912openalex-snapshot
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach
inferred← citeshttps://doi.org/10.1109/tcad.2021.3110807openalex-snapshot
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
inferred← citeshttps://doi.org/10.1109/tcad.2021.3111550openalex-snapshot
Digitally Assisted Mixed-Signal Circuit Security
inferred← citeshttps://doi.org/10.1109/tcad.2021.3138686openalex-snapshot
A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking
inferred← citeshttps://doi.org/10.1109/tcad.2022.3192793openalex-snapshot
Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis
inferred← citeshttps://doi.org/10.1109/tcad.2022.3215796openalex-snapshot
HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language
inferred← citeshttps://doi.org/10.1109/tcad.2022.3231174openalex-snapshot
RESCUE: Resilient, Scalable, High-Corruption, Compact-Key-Set Locking Framework
inferred← citeshttps://doi.org/10.1109/tcad.2023.3253428openalex-snapshot
On the Security of Sequential Logic Locking Against Oracle-Guided Attacks
inferred← citeshttps://doi.org/10.1109/tcsi.2017.2694968openalex-snapshot
Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases
inferred← citeshttps://doi.org/10.1109/tcsi.2021.3067319openalex-snapshot
NoPUF: A Novel PUF Design Framework Toward Modeling Attack Resistant PUFs
inferred← citeshttps://doi.org/10.1109/tcsi.2022.3214111openalex-snapshot
Anti-Piracy Design of RF Transceivers
inferred← citeshttps://doi.org/10.1109/tcsii.2020.3012869openalex-snapshot
IC Random Number Generator Exploiting Two Simultaneous Metastable Events of Tetrahedral Oscillators
inferred← citeshttps://doi.org/10.1109/tcsii.2020.3040725openalex-snapshot
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges
inferred← citeshttps://doi.org/10.1109/tcsii.2021.3113035openalex-snapshot
OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3165709openalex-snapshot
RF Transceiver Security Against Piracy Attacks
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