On the public citation graph

Real-Time Computing on Multicore Processors

0 signed · 28 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-24686-2_8openalex-snapshot
Real-Time Virtual Machines for Avionics Software Porting and Development
inferredcites →https://doi.org/10.1109/compsac.2014.54openalex-snapshot
Integrated Modular Avionics (IMA) Partition Scheduling with Conflict-Free I/O for Multicore Avionics Systems
inferredcites →https://doi.org/10.1109/ecrts.2015.23openalex-snapshot
WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence
inferredcites →https://doi.org/10.1109/rtas.2013.6531078openalex-snapshot
Real-time cache management framework for multi-core architectures
inferredcites →https://doi.org/10.1109/rtas.2013.6531079openalex-snapshot
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms
inferredcites →https://doi.org/10.1109/rtas.2014.6925998openalex-snapshot
Bounding memory interference delay in COTS-based multi-core systems
inferredcites →https://doi.org/10.1109/rtas.2014.6925999openalex-snapshot
PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms
inferredcites →https://doi.org/10.1145/1347375.1347389openalex-snapshot
The worst-case execution-time problem—overview of methods and survey of tools

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-032-06343-4_5openalex-snapshot
OpenMP-RT: Pragma Support for Scheduling Periodic Real-Time Tasks
inferred← citeshttps://doi.org/10.1007/978-3-032-28079-4_11openalex-snapshot
Multicore Scheduling for Large Safety-Critical Applications: Beyond Single-Core Equivalence
inferred← citeshttps://doi.org/10.1007/s11241-020-09343-2openalex-snapshot
Estimating WCET using prediction models to compute fitness function of a genetic algorithm
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102857openalex-snapshot
X-Stream: Accelerating streaming segments on MPSoCs for real-time applications
inferred← citeshttps://doi.org/10.1109/ets.2016.7519309openalex-snapshot
Automotive embedded software architecture in the multi-core age
inferred← citeshttps://doi.org/10.1109/hpec.2017.8091059openalex-snapshot
WCET analysis of the shared data cache in integrated CPU-GPU architectures
inferred← citeshttps://doi.org/10.1109/les.2022.3143719openalex-snapshot
Global Voltage Scaling Across Multiple Cores for Real-Time Workloads
inferred← citeshttps://doi.org/10.1109/rtas.2017.1openalex-snapshot
A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.000-3openalex-snapshot
A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00006openalex-snapshot
The Potential of Programmable Logic in the Middle: Cache Bleaching
inferred← citeshttps://doi.org/10.1109/rtas65571.2025.00032openalex-snapshot
Arm Dynamiq Shared Unit and Real-Time: An Empirical Evaluation
inferred← citeshttps://doi.org/10.1109/rtss.2018.00040openalex-snapshot
Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems
inferred← citeshttps://doi.org/10.1142/s021812662050005xopenalex-snapshot
Determination of Worst-Case Data Using an Adaptive Surrogate Model for Real-Time System
inferred← citeshttps://doi.org/10.1145/3203407openalex-snapshot
Schedulability Analysis of Tasks with Corunner-Dependent Execution Times
inferred← citeshttps://doi.org/10.1145/3371088openalex-snapshot
Virtual timeline: a formal abstraction for verifying preemptive schedulers with temporal isolation
inferred← citeshttps://doi.org/10.1145/3563290openalex-snapshot
Compositional virtual timelines: verifying dynamic-priority partitions with algorithmic temporal isolation
inferred← citeshttps://doi.org/10.1145/3652032.3657574openalex-snapshot
OpenMP-RT: Native Pragma Support for Real-Time Tasks and Synchronization with LLVM under Linux
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116364openalex-snapshot
Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems
inferred← citeshttps://doi.org/10.3384/lic.diva-134427openalex-snapshot
Timing Predictability in Future Multi-Core Avionics Systems
inferred← citeshttps://doi.org/10.48550/arxiv.1912.10959openalex-snapshot
Virtual Gang based Scheduling of Real-Time Tasks on Multicore Platforms
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.