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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1023/b:supe.0000014800.27383.8fopenalex-snapshot
Dynamic Partitioning of Shared Cache Memory
inferredcites →https://doi.org/10.1109/12.165388openalex-snapshot
Optimal partitioning of cache memory
inferredcites →https://doi.org/10.1109/hpca.2002.995703openalex-snapshot
A new memory monitoring scheme for memory-aware scheduling and partitioning
inferredcites →https://doi.org/10.1109/hpca.2004.10017openalex-snapshot
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2006.5openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1109/pact.2004.1342546openalex-snapshot
Fair cache sharing and partitioning in a chip multiprocessor architecture
inferredcites →https://doi.org/10.1109/real.1997.641291openalex-snapshot
A resource allocation model for QoS management
inferredcites →https://doi.org/10.1145/1024393.1024415openalex-snapshot
Dynamic tracking of page miss ratio curve for memory management
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1150019.1136501openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1152154.1152161openalex-snapshot
Communist, utilitarian, and capitalist cache policies on CMPs
inferredcites →https://doi.org/10.1145/357980.357997openalex-snapshot
The working set model for program behavior
inferredcites →https://doi.org/10.1145/363095.363141openalex-snapshot
The working set model for program behavior
inferredcites →https://doi.org/10.1145/781027.781076openalex-snapshot
Using SimPoint for accurate and efficient simulation
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies
inferredcites →https://doi.org/10.5555/1025127.1026001openalex-snapshot
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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PCASA: Probabilistic control-adjusted Selective Allocation for shared caches
inferred← citeshttps://doi.org/10.1109/date.2012.6176518openalex-snapshot
Dynamic cache management in multi-core architectures through run-time adaptation
inferred← citeshttps://doi.org/10.1109/dcabes.2012.39openalex-snapshot
An Improved Multi-core Shared Cache Replacement Algorithm
inferred← citeshttps://doi.org/10.1109/dcabes.2012.67openalex-snapshot
A Novel Online Measure of Cache Utility Efficiency in Chip Multiprocessor
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Classification-Based Unified Cache Replacement via Partitioned Victim Address History
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RaceR: A Thread Mapping Algorithm for Race Reduction in Multi-Level Shared Caches
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Automatic Quality of Service Control in Multi-core Systems using Cache Partitioning
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OMBM: Optimized Memory Bandwidth Management for Ensuring QoS and High Server Utilization
inferred← citeshttps://doi.org/10.1109/fpt.2010.5681447openalex-snapshot
A configurable framework for investigating workload execution
inferred← citeshttps://doi.org/10.1109/hipc.2014.7116707openalex-snapshot
Balancing context switch penalty and response time with elastic time slicing
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133713openalex-snapshot
SCALE: Secure and Scalable Cache Partitioning
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658653openalex-snapshot
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798260openalex-snapshot
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798261openalex-snapshot
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416638openalex-snapshot
DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416641openalex-snapshot
ESP-NUCA: A low-cost adaptive Non-Uniform Cache Architecture
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416644openalex-snapshot
StimulusCache: Boosting performance of chip multiprocessors with excess cache
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A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems
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Understanding how off-chip memory bandwidth partitioning in Chip Multiprocessors affects system performance
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749731openalex-snapshot
CloudCache: Expanding and shrinking private caches
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749732openalex-snapshot
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749733openalex-snapshot
NUcache: An efficient multicore cache organization based on Next-Use distance
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749757openalex-snapshot
ACCESS: Smart scheduling for asymmetric cache CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168947openalex-snapshot
TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169030openalex-snapshot
Decoupled dynamic cache segmentation
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169036openalex-snapshot
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522315openalex-snapshot
Modeling performance variation due to cache sharing
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522318openalex-snapshot
Optimizing Google's warehouse scale computers: The NUMA experience
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522354openalex-snapshot
Tiered-latency DRAM: A low latency and low cost DRAM architecture
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835954openalex-snapshot
Improving cache performance using read-write partitioning
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835960openalex-snapshot
Reducing the cost of persistence for nonvolatile heaps in end user devices
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056022openalex-snapshot
Talus: A simple way to remove cliffs in cache performance
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056026openalex-snapshot
XChange: A market-based approach to scalable dynamic multi-resource allocation in multicore architectures
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056061openalex-snapshot
Scaling distributed cache hierarchies through computation and data co-scheduling
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446067openalex-snapshot
Modeling cache performance beyond LRU
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446095openalex-snapshot
Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446100openalex-snapshot
Energy-efficient address translation
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446102openalex-snapshot
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family
inferred← citeshttps://doi.org/10.1109/hpca.2017.22openalex-snapshot
Cooper: Task Colocation with Cooperative Games
inferred← citeshttps://doi.org/10.1109/hpca.2017.65openalex-snapshot
SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support
inferred← citeshttps://doi.org/10.1109/hpca.2018.00019openalex-snapshot
KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores
inferred← citeshttps://doi.org/10.1109/hpca.2018.00022openalex-snapshot
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
inferred← citeshttps://doi.org/10.1109/hpca.2018.00027openalex-snapshot
Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls
inferred← citeshttps://doi.org/10.1109/hpca.2018.00030openalex-snapshot
Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management
inferred← citeshttps://doi.org/10.1109/hpca.2018.00034openalex-snapshot
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime
inferred← citeshttps://doi.org/10.1109/hpca.2018.00062openalex-snapshot
Characterizing Resource Sensitivity of Database Workloads
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Enhancing Server Efficiency in the Face of Killer Microseconds
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P-OPT: Practical Optimal Cache Replacement for Graph Analytics
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Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures
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Adaptive Security Support for Heterogeneous Memory on GPUs
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MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks
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Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather
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Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System
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Towards Online Application Cache Behaviors Identification in CMPs
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