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A Predictive Performance Model for Superscalar Processors
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Outgoing claims: the papers this work cites, builds on, or argues with.
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inferredcites →https://doi.org/10.1109/cgo.2006.37openalex-snapshot
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Construction and Use of Linear Regression Models for Processor Performance Analysis
inferredcites →https://doi.org/10.1109/isca.2000.854379openalex-snapshot
HLS: combining statistical and symbolic simulation to guide microprocessor designs
inferredcites →https://doi.org/10.1109/isca.2001.937455openalex-snapshot
Measuring experimental error in microprocessor simulation
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A first-order superscalar processor model
inferredcites →https://doi.org/10.1109/isca.2004.1310787openalex-snapshot
Control flow modeling in statistical simulation for accurate and efficient processor design studies
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1111/j.1467-985x.2010.00646_6.xopenalex-snapshot
The Elements of Statistical Learning: Data Mining, Inference, and Prediction
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Cross-architecture performance predictions for scientific applications using parameterized models
inferredcites →https://doi.org/10.1145/1028176.1006729openalex-snapshot
A First-Order Superscalar Processor Model
inferredcites →https://doi.org/10.1145/1028176.1006730openalex-snapshot
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies
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Theoretical modeling of superscalar processor performance
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A Comparison of Three Methods for Selecting Values of Input Variables in the Analysis of Output from a Computer Code
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A Comparison of Three Methods for Selecting Values of Input Variables in the Analysis of Output from a Computer Code
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inferred← citeshttps://doi.org/10.1007/978-1-4419-9551-3_10openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-031-01727-8openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-3-540-93799-9_7openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-90-481-3177-8_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/978-94-007-1488-5_4openalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s10766-012-0220-yopenalex-snapshot
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inferred← citeshttps://doi.org/10.1007/s11227-020-03475-9openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/b978-0-12-415844-3.00003-6openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.compeleceng.2020.106965openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.micpro.2012.07.006openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.peva.2009.03.004openalex-snapshot
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inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.03.004openalex-snapshot
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inferred← citeshttps://doi.org/10.1049/iet-cdt.2016.0148openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icsamos.2008.4664858openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/igcc.2016.7892589openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iiswc.2011.6114192openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ipdps.2018.00086openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca.2014.6853198openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isda.2012.6416643openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2008.4510745openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2008.4510747openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2011.5762738openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2012.6189201openalex-snapshot
Stargazer: Automated regression-based GPU design space exploration
inferred← citeshttps://doi.org/10.1109/ispass.2012.6189202openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2017.7975272openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isvlsi.2010.67openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/jproc.2018.2817118openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mascot.2008.4770557openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mascot.2009.5366283openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro.2007.21openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro.2010.14openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mm.2007.61openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mwscas.2007.4488749openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/norcas64408.2024.10752440openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/samos.2012.6404177openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/samos.2015.7363659openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/samos.2016.7818338openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/sasp.2008.4570789openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2007.70817openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tcad.2009.2028681openalex-snapshot
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inferred← citeshttps://doi.org/10.5121/ijnsa.2015.7302openalex-snapshot
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