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Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/spe.572openalex-snapshot
Microbenchmarks for determining branch predictor organization
inferredcites →https://doi.org/10.1007/978-1-4613-1453-0_9openalex-snapshot
Instruction Level Power Analysis and Optimization of Software
inferredcites →https://doi.org/10.1016/s1383-7621(98)00053-8openalex-snapshot
Bounds modelling and compiler optimizations for superscalar performance tuning
inferredcites →https://doi.org/10.1093/comjnl/bxs116openalex-snapshot
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up
inferredcites →https://doi.org/10.1109/12.2202openalex-snapshot
Benchmark synthesis using the LRU cache hit function
inferredcites →https://doi.org/10.1109/2.675637openalex-snapshot
Calibration of microprocessor performance models
inferredcites →https://doi.org/10.1109/43.736182openalex-snapshot
Microprocessor power estimation using profile-driven program synthesis
inferredcites →https://doi.org/10.1109/asscc.2008.4708718openalex-snapshot
A sub 2W low power IA Processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS
inferredcites →https://doi.org/10.1109/greencomp.2010.5598313openalex-snapshot
Portable, scalable, per-core power estimation for intelligent resource management
inferredcites →https://doi.org/10.1109/hpca.2008.4658642openalex-snapshot
Automated microprocessor stressmark generation
inferredcites →https://doi.org/10.1109/hpca.2012.6169042openalex-snapshot
WEST: Cloning data cache behavior using Stochastic Traces
inferredcites →https://doi.org/10.1109/iiswc.2005.1526007openalex-snapshot
Efficient power analysis using synthetic testcases
inferredcites →https://doi.org/10.1109/iiswc.2006.302734openalex-snapshot
Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks
inferredcites →https://doi.org/10.1109/iiswc.2010.5650208openalex-snapshot
Benchmark synthesis for architecture and compiler exploration
inferredcites →https://doi.org/10.1109/ipdps.2010.5470358openalex-snapshot
Servet: A benchmark suite for autotuning on multicore clusters
inferredcites →https://doi.org/10.1109/islped.2011.5993645openalex-snapshot
Automated di/dt stressmark generation for microprocessor power delivery networks
inferredcites →https://doi.org/10.1109/ispass.2006.1620800openalex-snapshot
Automatic testcase synthesis and performance model validation for highperformance PowerPC processors
inferredcites →https://doi.org/10.1109/ispass.2007.363746openalex-snapshot
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
inferredcites →https://doi.org/10.1109/ispass.2009.4919652openalex-snapshot
Experiment flows and microbenchmarks for reverse engineering of branch predictor structures
inferredcites →https://doi.org/10.1109/isscc.2010.5433919openalex-snapshot
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
inferredcites →https://doi.org/10.1109/jssc.2005.859894openalex-snapshot
The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor
inferredcites →https://doi.org/10.1109/jssc.2008.2007170openalex-snapshot
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS
inferredcites →https://doi.org/10.1109/jssc.2010.2079410openalex-snapshot
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation
inferredcites →https://doi.org/10.1109/micro.2003.1253186openalex-snapshot
Runtime power monitoring in high-end processors: methodology and empirical data
inferredcites →https://doi.org/10.1109/micro.2010.34openalex-snapshot
AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors
inferredcites →https://doi.org/10.1109/mm.2011.36openalex-snapshot
Automated Full-System Power Characterization
inferredcites →https://doi.org/10.1109/tc.2011.47openalex-snapshot
Complete System Power Estimation Using Processor Performance Events
inferredcites →https://doi.org/10.1109/tc.2012.97openalex-snapshot
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs
inferredcites →https://doi.org/10.1145/1088149.1088164openalex-snapshot
Improved automatic testcase synthesis for performance model validation
inferredcites →https://doi.org/10.1145/1146909.1147053openalex-snapshot
A systematic method for functional unit power estimation in microprocessors
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1289927.1289945openalex-snapshot
Accurate on-line prediction of processor and memoryenergy usage under voltage scaling
inferredcites →https://doi.org/10.1145/1400112.1400115openalex-snapshot
Distilling the essence of proprietary workloads into miniature benchmarks
inferredcites →https://doi.org/10.1145/1577129.1577137openalex-snapshot
Real time power estimation and thread scheduling via performance counters
inferredcites →https://doi.org/10.1145/1810085.1810108openalex-snapshot
Decomposable and responsive power models for multicore processors using performance counters
inferredcites →https://doi.org/10.1145/1854273.1854281openalex-snapshot
Power and thermal characterization of POWER6 system
inferredcites →https://doi.org/10.1145/1854273.1854282openalex-snapshot
System-level max power (SYMPO)
inferredcites →https://doi.org/10.1145/2063384.2063455openalex-snapshot
MAximum Multicore POwer (MAMPO)
inferredcites →https://doi.org/10.1145/305138.305211openalex-snapshot
Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications
inferredcites →https://doi.org/10.1145/781027.781048openalex-snapshot
Run-time modeling and estimation of operating system power consumption
inferredcites →https://doi.org/10.1145/885651.781048openalex-snapshot
Run-time modeling and estimation of operating system power consumption
inferredcites →https://doi.org/10.1147/jrd.2011.2114250openalex-snapshot
Adaptive energy-management features of the IBM POWER7 chip
inferredcites →https://doi.org/10.1147/jrd.2011.2127330openalex-snapshot
IBM POWER7 multicore server processor
inferredcites →https://doi.org/10.5555/2016802.2016860openalex-snapshot
Automated di/dt stressmark generation for microprocessor power delivery networks
inferredcites →https://doi.org/10.5555/956417.956567openalex-snapshot
Runtime power monitoring in high-end processors: methodology and empirical data
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Test Generation for Detection of Malicious Parametric Variations
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Data Center Energy Consumption Modeling: A Survey
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Power and Energy Characterization of an Open Source 25-Core Manycore Processor
inferred← citeshttps://doi.org/10.1109/hpca.2019.00031openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408462openalex-snapshot
SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581266openalex-snapshot
Characterization and mitigation of power contention across multiprogrammed workloads
inferred← citeshttps://doi.org/10.1109/iiswc.2018.8573473openalex-snapshot
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00012openalex-snapshot
Energy Efficiency Boost in the AI-Infused POWER10 Processor
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00045openalex-snapshot
Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation
inferred← citeshttps://doi.org/10.1109/islped.2015.7273513openalex-snapshot
FreqLeak: A frequency step based method for efficient leakage power characterization in a system
inferred← citeshttps://doi.org/10.1109/islped52811.2021.9502485openalex-snapshot
An Instruction-Level Power and Energy Model for the Rocket Chip Generator
inferred← citeshttps://doi.org/10.1109/ispass.2018.00014openalex-snapshot
Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs
inferred← citeshttps://doi.org/10.1109/ispass.2019.00009openalex-snapshot
GeST: An Automatic Framework For Generating CPU Stress-Tests
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MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing
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SAGA: A Surrogate Assisted Genetic Algorithm for Fast CPU Power Virus Generation
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Embedded two phase liquid cooling for increasing computational efficiency
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Thermal model for embedded two-phase liquid cooled microprocessor
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Microfluidic two-phase cooling of a high power microprocessor part B: Test and characterization
inferred← citeshttps://doi.org/10.1109/itherm54085.2022.9899530openalex-snapshot
Microprocessor Performance with Multiple Cooling Approaches
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IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems
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Dynamic Guardband Features of the IBM z17 System
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Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities
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A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events
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SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers
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DStress: Automatic Synthesis of DRAM Reliability Stress Viruses using Genetic Algorithms
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NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators
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Machine learning techniques for taming the complexity of modern hardware design
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