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Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache

https://doi.org/10.1109/rtas.2006.24
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1023/a:1008145215849openalex-snapshot
Timing Analysis for Instruction Caches
inferredcites →https://doi.org/10.1109/dac.1997.597135openalex-snapshot
A Task-level Hierarchical Memory Model For System Synthesis Of Multiprocessors
inferredcites →https://doi.org/10.1109/dsd.2004.1333254openalex-snapshot
Long term trends for embedded system design
inferredcites →https://doi.org/10.1109/micro.1996.566459openalex-snapshot
Wrong-path instruction prefetching
inferredcites →https://doi.org/10.1109/real.1993.393511openalex-snapshot
A dual-mode instruction prefetch scheme for improved worst case and average case program execution times
inferredcites →https://doi.org/10.1109/real.2003.1253251openalex-snapshot
Evolving real-time systems using hierarchical scheduling and concurrency analysis
inferredcites →https://doi.org/10.1109/rttas.2002.1137388openalex-snapshot
A measurement-based analysis of the real-time performance of linux
inferredcites →https://doi.org/10.1109/wwc.2001.15openalex-snapshot
MiBench: A free, commercially representative embedded benchmark suite
inferredcites →https://doi.org/10.1145/1023833.1023839openalex-snapshot
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches
inferredcites →https://doi.org/10.1145/1065910.1065918openalex-snapshot
Preventing interrupt overload
inferredcites →https://doi.org/10.1145/266021.266053openalex-snapshot
A task-level hierarchical memory model for system synthesis of multiprocessors
inferredcites →https://doi.org/10.1145/268424.268464openalex-snapshot
Memory data organization for improved cache performance in embedded processor applications
inferredcites →https://doi.org/10.1145/337292.337523openalex-snapshot
Application-specific memory management for embedded systems using software-controlled caches
inferredcites →https://doi.org/10.1145/358274.358283openalex-snapshot
Dhrystone
inferredcites →https://doi.org/10.1145/581888.581891openalex-snapshot
An optimal memory allocation scheme for scratch-pad-based embedded systems
inferredcites →https://doi.org/10.1145/940071.940098openalex-snapshot
Deadline analysis of interrupt-driven software
inferredcites →https://doi.org/10.1145/988952.989039openalex-snapshot
Cluster miss prediction for instruction caches in embedded networking applications
inferredcites →https://doi.org/10.1201/9781482280845openalex-snapshot
Real-Time Embedded Multithreading
inferredcites →https://doi.org/10.3182/20020721-6-es-1901.00974openalex-snapshot
DYNAMIC USE OF LOCKING CACHES IN MULTITASK, PREEMPTIVE REAL-TIME SYSTEMS
inferredcites →https://doi.org/10.5555/243846.243882openalex-snapshot
Wrong-path instruction prefetching

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-540-89740-8_3openalex-snapshot
Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture
inferred← citeshttps://doi.org/10.1109/rtss.2007.10openalex-snapshot
Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts
inferred← citeshttps://doi.org/10.1109/rtss.2007.28openalex-snapshot
ANDES: An ANalysis-Based DEsign Tool for Wireless Sensor Networks
inferred← citeshttps://doi.org/10.1109/tc.2010.119openalex-snapshot
On Improving Real-Time Interrupt Latencies of Hybrid Operating Systems with Two-Level Hardware Interrupts
inferred← citeshttps://doi.org/10.1109/tc.2010.44openalex-snapshot
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time
inferred← citeshttps://doi.org/10.1109/tpds.2009.97openalex-snapshot
Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture
inferred← citeshttps://doi.org/10.1145/1457246.1457253openalex-snapshot
Analyzing the worst-case execution time for instruction caches with prefetching
inferred← citeshttps://doi.org/10.1145/1721695.1721708openalex-snapshot
Interrupt handler migration and direct interrupt scheduling for rapid scheduling of interrupt-driven tasks
inferred← citeshttps://doi.org/10.11591/eei.v10i3.2526openalex-snapshot
Embedded operating system and industrial applications: a review
inferred← citeshttps://doi.org/10.4236/jsea.2013.61003openalex-snapshot
Microkernel Development for Embedded Systems
inferred← citeshttps://doi.org/10.4236/jsea.2014.71003openalex-snapshot
Analysis and Programming of Kernel for Embedded Systems
inferred← citeshttps://doi.org/10.5626/jcse.2009.3.1.059openalex-snapshot
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94621openalex-snapshot
Software caching techniques and hardware optimizations for on-chip local memories
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