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Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11241-005-0507-9openalex-snapshot
Measuring the Performance of Schedulability Tests
inferredcites →https://doi.org/10.1016/0166-5316(82)90024-4openalex-snapshot
On the complexity of fixed-priority scheduling of periodic, real-time tasks
inferredcites →https://doi.org/10.1016/j.microrel.2010.04.024openalex-snapshot
On-chip reliability monitors for measuring circuit degradation
inferredcites →https://doi.org/10.1049/sej.1993.0034openalex-snapshot
Applying new scheduling theory to static priority pre-emptive scheduling
inferredcites →https://doi.org/10.1109/aspdac.2012.6165040openalex-snapshot
RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware
inferredcites →https://doi.org/10.1109/date.2009.5090632openalex-snapshot
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
inferredcites →https://doi.org/10.1109/date.2011.5763249openalex-snapshot
Aging-aware timing analysis and optimization considering path sensitization
inferredcites →https://doi.org/10.1109/ecrts.2004.7openalex-snapshot
Biasing effects in schedulability measures
inferredcites →https://doi.org/10.1109/emrts.2004.1311021openalex-snapshot
Biasing effects in schedulability measures
inferredcites →https://doi.org/10.1109/iccad.2010.5654309openalex-snapshot
Aging analysis at gate and macro cell level
inferredcites →https://doi.org/10.1109/islped.2011.5993672openalex-snapshot
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
inferredcites →https://doi.org/10.1109/isqed.2009.4810264openalex-snapshot
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
inferredcites →https://doi.org/10.1109/isscc.2007.373409openalex-snapshot
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging
inferredcites →https://doi.org/10.1109/isscc.2007.373462openalex-snapshot
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor
inferredcites →https://doi.org/10.1109/mm.2011.29openalex-snapshot
Introducing the Adaptive Energy Management Features of the Power7 Chip
inferredcites →https://doi.org/10.1109/real.1989.63567openalex-snapshot
The rate monotonic scheduling algorithm: exact characterization and average case behavior
inferredcites →https://doi.org/10.1109/real.1990.128748openalex-snapshot
Fixed priority scheduling of periodic task sets with arbitrary deadlines
inferredcites →https://doi.org/10.1109/tcad.2005.862751openalex-snapshot
First-Order Incremental Block-Based Statistical Timing Analysis
inferredcites →https://doi.org/10.1145/1629911.1629915openalex-snapshot
Circuit techniques for dynamic variation tolerance
inferredcites →https://doi.org/10.1145/1629911.1630092openalex-snapshot
Process variation characterization of chip-level multiprocessors
inferredcites →https://doi.org/10.1145/2039370.2039408openalex-snapshot
Reliable software for unreliable hardware
inferredcites →https://doi.org/10.1145/2155620.2155622openalex-snapshot
Active management of timing guardband to save energy in POWER7
inferredcites →https://doi.org/10.1145/321738.321743openalex-snapshot
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
inferredcites →https://doi.org/10.5555/1874620.1874635openalex-snapshot
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms
inferredcites →https://doi.org/10.5555/2016802.2016894openalex-snapshot
A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems
inferredcites →https://doi.org/10.5555/2133429.2133444openalex-snapshot
Aging analysis at gate and macro cell level
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Reliable CPS Design for Unreliable Hardware Platforms
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Building Safe Autonomous Systems Using Imperfect Components
inferred← citeshttps://doi.org/10.1007/s11227-020-03326-7openalex-snapshot
TAMER: an adaptive task allocation method for aging reduction in multi-core embedded real-time systems
inferred← citeshttps://doi.org/10.1109/cpsna.2015.16openalex-snapshot
Reliable CPS Design for Mitigating Semiconductor and Battery Aging in Electric Vehicles
inferred← citeshttps://doi.org/10.1109/hpcsim.2015.7237093openalex-snapshot
Investigation of DVFS based dynamic reliability management for chip multiprocessors
inferred← citeshttps://doi.org/10.1109/iolts.2019.8854444openalex-snapshot
Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores
inferred← citeshttps://doi.org/10.1109/itc-asia.2018.00015openalex-snapshot
MTTF-Aware Reliability Task Scheduling for PIM-Based Heterogeneous Computing System
inferred← citeshttps://doi.org/10.1109/mdat.2016.2573598openalex-snapshot
Automotive Cyber–Physical Systems: A Tutorial Introduction
inferred← citeshttps://doi.org/10.1109/rtas.2013.6531099openalex-snapshot
Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations
inferred← citeshttps://doi.org/10.1109/rtss.2014.24openalex-snapshot
Battery- and Aging-Aware Embedded Control Systems for Electric Vehicles
inferred← citeshttps://doi.org/10.1109/tc.2015.2417554openalex-snapshot
Cross-Layer Software Dependability on Unreliable Hardware
inferred← citeshttps://doi.org/10.1109/tc.2018.2848276openalex-snapshot
Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197527openalex-snapshot
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures
inferred← citeshttps://doi.org/10.1145/2463209.2488857openalex-snapshot
Reliable on-chip systems in the nano-era
inferred← citeshttps://doi.org/10.1145/3660633openalex-snapshot
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs
inferred← citeshttps://doi.org/10.1145/3797248.3816062openalex-snapshot
Carbon at the Memory Wall: Lifecycle and Aging-Aware Analysis of Processing-in-DRAM LLM Servers
inferred← citeshttps://doi.org/10.1561/1000000045openalex-snapshot
Resource-aware Automotive Control Systems Design: A Cyber-Physical Systems Approach
inferred← citeshttps://doi.org/10.32657/10356/144282openalex-snapshot
Scalable techniques for extending lifetime reliability of manycore systems
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