On the public citation graph

Monolithic 3D integration: A powerful alternative to classical 2D scaling

https://doi.org/10.1109/s3s.2014.7028194
0 signed · 65 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/essderc.2014.6948770openalex-snapshot
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration
inferredcites →https://doi.org/10.1109/iedm.2008.4796670openalex-snapshot
Setting up 3D sequential integration for back-illuminated CMOS image sensors with highly miniaturized pixels with low temperature fully depleted SOI transistors
inferredcites →https://doi.org/10.1109/iedm.2013.6724540openalex-snapshot
Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities
inferredcites →https://doi.org/10.1109/iitc.2014.6831837openalex-snapshot
3D sequential integration opportunities and technology optimization
inferredcites →https://doi.org/10.1109/iwjt.2012.6212810openalex-snapshot
Laser Thermal Annealing: Enabling ultra-low thermal budget processes for 3D junctions formation and devices
inferredcites →https://doi.org/10.1109/iwjt.2014.6842057openalex-snapshot
Insights in accesses optimization for nFET low temperature Fully Depleted Silicon On Insulator devices
inferredcites →https://doi.org/10.1109/jetcas.2012.2223593openalex-snapshot
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS
inferredcites →https://doi.org/10.1149/06405.0381ecstopenalex-snapshot
(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration
inferredcites →https://doi.org/10.1149/1.2982853openalex-snapshot
Enabling 3D Monolithic Integration

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.4615575openalex-extracted
Characteristics of High-Order Silane Based Si and Sige Epitaxial Growth Under 600°C
inferred← citeshttps://doi.org/10.1002/9781119069225.ch1-4openalex-snapshot
Three‐Dimensional Integration of Ge and Two‐Dimensional Materials for One‐Dimensional Devices
inferred← citeshttps://doi.org/10.1002/adfm.74729openalex-snapshot
Atomic Layer Deposition in Transistors and Monolithic 3D Integration
inferred← citeshttps://doi.org/10.1002/aelm.202500682openalex-snapshot
Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks
inferred← citeshttps://doi.org/10.1007/978-3-030-79827-7_32openalex-snapshot
Memristive/CMOS Devices for Neuromorphic Applications
inferred← citeshttps://doi.org/10.1007/978-3-319-22093-2_3openalex-snapshot
Monolithic 3D Integration
inferred← citeshttps://doi.org/10.1007/978-3-319-54714-5_8openalex-snapshot
Conclusions
inferred← citeshttps://doi.org/10.1007/978-981-16-7487-7_4openalex-snapshot
Interconnect and Integration Technology
inferred← citeshttps://doi.org/10.1007/s11664-023-10670-wopenalex-snapshot
Ultrathin GaN Crystal Realized Through Nitrogen Substitution of Layered GaS
inferred← citeshttps://doi.org/10.1007/s12274-021-3459-zopenalex-snapshot
Carbon nanotube transistor technology for More-Moore scaling
inferred← citeshttps://doi.org/10.1007/s40820-025-01898-8openalex-snapshot
Beyond the Silicon Plateau: A Convergence of Novel Materials for Transistor Evolution
inferred← citeshttps://doi.org/10.1038/s41699-024-00509-1openalex-snapshot
2D materials-based 3D integration for neuromorphic hardware
inferred← citeshttps://doi.org/10.1038/s44287-024-00038-5openalex-snapshot
3D integration of 2D electronics
inferred← citeshttps://doi.org/10.1080/14686996.2017.1364975openalex-snapshot
Intermetallic compounds in 3D integrated circuits technology: a brief review
inferred← citeshttps://doi.org/10.1109/access.2023.3305593openalex-snapshot
On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits
inferred← citeshttps://doi.org/10.1109/ectc51687.2025.00305openalex-snapshot
Capping Layers for Enhanced Crystallinity of Single-Crystal Germanium on Insulator in Monolithic 3D ICs
inferred← citeshttps://doi.org/10.1109/esscirc.2016.7598246openalex-snapshot
Delay partitioning helps reducing variability in 3DVLSI
inferred← citeshttps://doi.org/10.1109/essderc.2016.7599590openalex-snapshot
Delay partitioning helps reducing variability in 3DVLSI
inferred← citeshttps://doi.org/10.1109/essderc.2018.8486862openalex-snapshot
InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance
inferred← citeshttps://doi.org/10.1109/ets.2016.7519311openalex-snapshot
A design-for-test solution for monolithic 3D integrated circuits
inferred← citeshttps://doi.org/10.1109/igsc64514.2024.00022openalex-snapshot
Energy-Efficient Dataflow Design for Monolithic 3D Systolic Arrays with Resistive RAM
inferred← citeshttps://doi.org/10.1109/iseda59274.2023.10218417openalex-snapshot
Thermal Evaluation for Monolithic 3D Integrated Circuits Based on Gate-all-Around Transistors
inferred← citeshttps://doi.org/10.1109/itc-asia53059.2021.9808837openalex-snapshot
Testing and Fault-Localization Solutions for Monolithic 3D ICs
inferred← citeshttps://doi.org/10.1109/jeds.2018.2802840openalex-snapshot
Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials
inferred← citeshttps://doi.org/10.1109/jeds.2019.2928471openalex-snapshot
InGaAs FinFETs 3-D Sequentially Integrated on FDSOI Si CMOS With Record Performance
inferred← citeshttps://doi.org/10.1109/led.2018.2889346openalex-snapshot
Low-Temperature Fabrication of High Quality Gate Insulator in Metal–Oxide–Semiconductor Capacitor Using Laser Annealing
inferred← citeshttps://doi.org/10.1109/led.2020.2971321openalex-snapshot
Photo-Responsible Synapse Using Ge Synaptic Transistors and GaAs Photodetectors
inferred← citeshttps://doi.org/10.1109/led.2024.3443512openalex-snapshot
First Experimental Demonstration of 3D-Stacked 2T0C DRAM Cells Based on Indium Tin Oxide Channel
inferred← citeshttps://doi.org/10.1109/led.2025.3549455openalex-snapshot
Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing
inferred← citeshttps://doi.org/10.1109/nano.2015.7388860openalex-snapshot
The nanodamascene process: A versatile fabrication technique for nanoelectronic applications
inferred← citeshttps://doi.org/10.1109/sispad.2018.8551699openalex-snapshot
Rapid and Holistic Technology Evaluation for Exploratory DTCO in Beyond 7nm Technologies
inferred← citeshttps://doi.org/10.1109/tcad.2021.3139310openalex-snapshot
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs
inferred← citeshttps://doi.org/10.1109/tcpmt.2015.2511082openalex-snapshot
A Simulation Tool for Rapid Investigation of Trends in 3-DIC Performance and Power Consumption
inferred← citeshttps://doi.org/10.1109/ted.2015.2479087openalex-snapshot
Sequential Lateral Solidification of Silicon Thin Films on Cu BEOL-Integrated Wafers for Monolithic 3-D Integration
inferred← citeshttps://doi.org/10.1109/ted.2017.2755662openalex-snapshot
Demonstration of 3-D SRAM Cell by 3-D Monolithic Integration of InGaAs n-FinFETs on FDSOI CMOS With Interlayer Contacts
inferred← citeshttps://doi.org/10.1109/ted.2018.2810304openalex-snapshot
Impact of Ground Plane Doping and Bottom-Gate Biasing on Electrical Properties in In0.53Ga0.47As-OI MOSFETs and Donor Wafer Reusability Toward Monolithic 3-D Integration With In0.53Ga0.47As Channel
inferred← citeshttps://doi.org/10.1109/ted.2024.3371422openalex-snapshot
High-Pressure Deuterium Annealing for Trap Passivation for a 3-D Integrated Structure
inferred← citeshttps://doi.org/10.1109/ted.2025.3619479openalex-snapshot
Monolithic Stacked IGZO 2T0C DRAM Cells With Divisional Optimization Scheme Achieving Ultralong Retention and Stable Multibit Operation
inferred← citeshttps://doi.org/10.1109/ted.2025.3635625openalex-snapshot
High-Performance Heterogeneous 3-D Sequential CFETs Using Pulsed Green Laser Annealing
inferred← citeshttps://doi.org/10.1109/tmscs.2018.2882433openalex-snapshot
A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3073070openalex-snapshot
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3450452openalex-snapshot
A Post-Bond ILV Test Method in Monolithic 3-D ICs
inferred← citeshttps://doi.org/10.1109/vts.2015.7116262openalex-snapshot
3D microelectronic with BEOL compatible devices
inferred← citeshttps://doi.org/10.1145/2902961.2903512openalex-snapshot
Leveraging 3D Technologies for Hardware Security
inferred← citeshttps://doi.org/10.1145/3439706.3446903openalex-snapshot
Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies
inferred← citeshttps://doi.org/10.1145/3473462openalex-snapshot
Design Automation and Test Solutions for Monolithic 3D ICs
inferred← citeshttps://doi.org/10.1155/2017/8613571openalex-snapshot
A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3713636/v1openalex-snapshot
Monolithic and heterogeneous three-dimensional (3D) integration of two-dimensional (2D) materials using dense vias
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473921openalex-snapshot
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits
inferred← citeshttps://doi.org/10.23919/date56975.2023.10137051openalex-snapshot
Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits
inferred← citeshttps://doi.org/10.3390/app112412151openalex-snapshot
Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation
inferred← citeshttps://doi.org/10.3390/mi10100637openalex-snapshot
Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory
inferred← citeshttps://doi.org/10.3390/mi13101625openalex-snapshot
A Monolithic 3-Dimensional Static Random Access Memory Containing a Feedback Field Effect Transistor
inferred← citeshttps://doi.org/10.3390/mi14101822openalex-snapshot
Investigation of the Electrical Coupling Effect for Monolithic 3-Dimensional Nonvolatile Memory Consisting of a Feedback Field-Effect Transistor Using TCAD
inferred← citeshttps://doi.org/10.70675/59849761zc042z49f3zab27z89699c428470openalex-snapshot
Design methodology and technology assessment for high-desnity 3D technologies
inferred← citeshttps://doi.org/10.70675/5c7b8d21z691ez4c91z9fa5z9a6f26557ca9openalex-snapshot
Intégration 3D des transistors à nanofils de silicium-germanium sur puces CMOS
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.