On the public citation graph

CellSs: a Programming Model for the Cell BE Architecture

0 signed · 149 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bfb0024763openalex-snapshot
Dip: A parallel program development environment
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1023/b:grid.0000024072.93701.f3openalex-snapshot
Programming Grid Applications with GRID Superscalar
inferredcites →https://doi.org/10.1109/isscc.2005.1493930openalex-snapshot
The design and implementation of a first-generation CELL processor
inferredcites →https://doi.org/10.1109/mc.2005.160openalex-snapshot
Chip makers turn to multicore processors
inferredcites →https://doi.org/10.1109/sc.2004.26openalex-snapshot
GPU Cluster for High Performance Computing
inferredcites →https://doi.org/10.1109/sc.2005.42openalex-snapshot
LU-GPU: Efficient Algorithms for Solving Dense Linear Systems on Graphics Hardware
inferredcites →https://doi.org/10.1145/125826.126138openalex-snapshot
A fast static scheduling algorithm for DAGs on an unbounded number of processors
inferredcites →https://doi.org/10.1145/635508.605416openalex-snapshot
Compiler optimization of scalar value communication between speculative threads
inferredcites →https://doi.org/10.1145/882262.882362openalex-snapshot
Cg
inferredcites →https://doi.org/10.1147/sj.451.0059openalex-snapshot
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture
inferredcites →https://doi.org/10.5555/844174.844189openalex-snapshot
Simulation of cloud dynamics on graphics hardware

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/cpe.3407openalex-snapshot
ActiveSpaces: Exploring dynamic code deployment for extreme scale data processing
inferred← citeshttps://doi.org/10.1007/978-3-319-05215-1_6openalex-snapshot
Hybrid Programming Using OpenSHMEM and OpenACC
inferred← citeshttps://doi.org/10.1007/978-3-319-11454-5_16openalex-snapshot
On the Roles of the Programmer, the Compiler and the Runtime System When Programming Accelerators in OpenMP
inferred← citeshttps://doi.org/10.1007/978-3-319-21909-7_9openalex-snapshot
Control Flow Usage to Improve Performance of Fragmented Programs Execution
inferred← citeshttps://doi.org/10.1007/978-3-540-69303-1_12openalex-snapshot
Loading OpenMP to Cell: An Effective Compiler Framework for Heterogeneous Multi-core Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-69303-1_6openalex-snapshot
Supporting OpenMP on Cell
inferred← citeshttps://doi.org/10.1007/978-3-540-70550-5_9openalex-snapshot
A Real-Time Programming Model for Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1007/978-3-540-73625-7_13openalex-snapshot
A Streaming Machine Description and Programming Model
inferred← citeshttps://doi.org/10.1007/978-3-540-77560-7_13openalex-snapshot
Drug Design Issues on the Cell BE
inferred← citeshttps://doi.org/10.1007/978-3-540-79561-2_10openalex-snapshot
Extending the OpenMP Tasking Model to Allow Dependent Tasks
inferred← citeshttps://doi.org/10.1007/978-3-540-92990-1_14openalex-snapshot
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications
inferred← citeshttps://doi.org/10.1007/978-3-642-02303-3_13openalex-snapshot
A Proposal to Extend the OpenMP Tasking Model for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1007/978-3-642-03138-0_36openalex-snapshot
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System
inferred← citeshttps://doi.org/10.1007/978-3-642-03869-3_83openalex-snapshot
Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades
inferred← citeshttps://doi.org/10.1007/978-3-642-11620-9_6openalex-snapshot
A Comparison of Three Commodity-Level Parallel Architectures: Multi-core CPU, Cell BE and GPU
inferred← citeshttps://doi.org/10.1007/978-3-642-14122-5_9openalex-snapshot
Automatic Calibration of Performance Models on Heterogeneous Multicore Architectures
inferred← citeshttps://doi.org/10.1007/978-3-642-14390-8_57openalex-snapshot
Optimization of FDTD Computations in a Streaming Model Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-15291-7_18openalex-snapshot
Exploiting Fine-Grained Parallelism on Cell Processors
inferred← citeshttps://doi.org/10.1007/978-3-642-19448-1_10openalex-snapshot
Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector
inferred← citeshttps://doi.org/10.1007/978-3-642-19595-2_13openalex-snapshot
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores
inferred← citeshttps://doi.org/10.1007/978-3-642-28151-8_18openalex-snapshot
Streaming Model Computation of the FDTD Problem
inferred← citeshttps://doi.org/10.1007/978-3-642-36036-7_8openalex-snapshot
OPELL and PM: A Case Study on Porting Shared Memory Programming Models to Accelerators Architectures
inferred← citeshttps://doi.org/10.1007/978-3-642-36949-0_16openalex-snapshot
Exploring Heterogeneous Scheduling Using the Task-Centric Programming Model
inferred← citeshttps://doi.org/10.1007/978-3-662-48096-0_2openalex-snapshot
Runtime-Aware Architectures
inferred← citeshttps://doi.org/10.1007/978-3-662-58834-5_6openalex-snapshot
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability
inferred← citeshttps://doi.org/10.1007/978-94-007-0638-5_10openalex-snapshot
A Distributed Hardware Algorithm for Scheduling Dependent Tasks on Multicore Architectures
inferred← citeshttps://doi.org/10.1007/s10069-008-0015-xopenalex-snapshot
Experiments in scientific computation on the PlayStation 3
inferred← citeshttps://doi.org/10.1007/s10766-008-0072-7openalex-snapshot
Supporting OpenMP on Cell
inferred← citeshttps://doi.org/10.1007/s10766-008-0073-6openalex-snapshot
Nebelung: Execution Environment for Transactional OpenMP
inferred← citeshttps://doi.org/10.1007/s10766-009-0101-1openalex-snapshot
A Proposal to Extend the OpenMP Tasking Model with Dependent Tasks
inferred← citeshttps://doi.org/10.1007/s10766-010-0132-7openalex-snapshot
ACOTES Project: Advanced Compiler Technologies for Embedded Streaming
inferred← citeshttps://doi.org/10.1007/s10766-010-0135-4openalex-snapshot
Extending OpenMP to Survive the Heterogeneous Multi-Core Era
inferred← citeshttps://doi.org/10.1007/s10766-010-0156-zopenalex-snapshot
Adaptive Task Pools: Efficiently Balancing Large Number of Tasks on Shared-address Spaces
inferred← citeshttps://doi.org/10.1007/s10766-012-0209-6openalex-snapshot
Parallel Smith-Waterman Comparison on Multicore and Manycore Computing Platforms with BSP++
inferred← citeshttps://doi.org/10.1007/s11227-015-1449-1openalex-snapshot
Design space exploration of hardware task superscalar architecture
inferred← citeshttps://doi.org/10.1007/s11265-007-0067-4openalex-snapshot
Exploring New Search Algorithms and Hardware for Phylogenetics: RAxML Meets the IBM Cell
inferred← citeshttps://doi.org/10.1007/s11265-008-0171-0openalex-snapshot
A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1007/s11265-016-1107-8openalex-snapshot
Implementation, Scheduling, and Adaptation of Partial Expansion Graphs on Multicore Platforms
inferred← citeshttps://doi.org/10.1007/s42514-020-00039-4openalex-snapshot
Parallel programming models for heterogeneous many-cores: a comprehensive survey
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.01.008openalex-snapshot
Parallel exact inference on the Cell Broadband Engine processor
inferred← citeshttps://doi.org/10.1016/j.parco.2007.09.004openalex-snapshot
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
inferred← citeshttps://doi.org/10.1016/j.procs.2013.05.197openalex-snapshot
Analysis of the Task Superscalar Architecture Hardware Design
inferred← citeshttps://doi.org/10.1016/j.sysarc.2010.10.008openalex-snapshot
Compiler-directed memory management for heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1109/acssc.2014.7094469openalex-snapshot
Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems
inferred← citeshttps://doi.org/10.1109/chinagrid.2010.41openalex-snapshot
A Multi-node MPI Implementation on the CellBE Processor
inferred← citeshttps://doi.org/10.1109/cisis.2010.147openalex-snapshot
Automatic Offloading of C++ for the Cell BE Processor: A Case Study Using Offload
inferred← citeshttps://doi.org/10.1109/cit.2010.492openalex-snapshot
cCell: A S2S Compiler with Profiling Support for the Cell BE Architecture
inferred← citeshttps://doi.org/10.1109/clustr.2007.4629221openalex-snapshot
Satisfying your dependencies with SuperMatrix
inferred← citeshttps://doi.org/10.1109/clustr.2008.4663765openalex-snapshot
A dependency-aware task-based programming environment for multi-core architectures
inferred← citeshttps://doi.org/10.1109/csa.2009.5404267openalex-snapshot
Model-Directed Multi-Level Parallelization for Multi-Task Programs on the Cell BE
inferred← citeshttps://doi.org/10.1109/cse-euc-dcabes.2016.190openalex-snapshot
Automatic Code Generation of Distributed Parallel Tasks
inferred← citeshttps://doi.org/10.1109/dfm.2013.13openalex-snapshot
The Flexible Preconditions Model for Macro-Dataflow Execution
inferred← citeshttps://doi.org/10.1109/esscirc.2008.4681893openalex-snapshot
A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals
inferred← citeshttps://doi.org/10.1109/fccm.2010.15openalex-snapshot
Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive
inferred← citeshttps://doi.org/10.1109/fpga4gpc.2016.7518530openalex-snapshot
μStreams: a tool for automated streaming pipeline generation on soft-core processors
inferred← citeshttps://doi.org/10.1109/fpl.2009.5272501openalex-snapshot
Building heterogeneous reconfigurable systems using threads
inferred← citeshttps://doi.org/10.1109/hipc.2009.5433205openalex-snapshot
CellMT: A cooperative multithreading library for the Cell/B.E.
inferred← citeshttps://doi.org/10.1109/hpcc.2008.134openalex-snapshot
A Profile-based Memory Access Optimizing Technology on CBE Architecture
inferred← citeshttps://doi.org/10.1109/hpcc.2008.9openalex-snapshot
A Fast Wavelet Based Implementation to Calculate Coulomb Potentials on the Cell/B.E.
inferred← citeshttps://doi.org/10.1109/hpcsim.2011.5999874openalex-snapshot
Creating HW/SW co-designed MPSoPC's from high level programming models
inferred← citeshttps://doi.org/10.1109/hpec.2015.7322452openalex-snapshot
Heterogeneous work-stealing across CPU and DSP cores
inferred← citeshttps://doi.org/10.1109/iccie.2009.5223486openalex-snapshot
Parallel solution of the pooling problem with application to the Cell Broadband Engine Architecture
inferred← citeshttps://doi.org/10.1109/iccsa.2008.63openalex-snapshot
SysCellC: SystemC on Cell
inferred← citeshttps://doi.org/10.1109/icimia48430.2020.9074866openalex-snapshot
Prediction Model of an HPC Application on CPU-GPU Cluster using Machine Learning Techniques
inferred← citeshttps://doi.org/10.1109/icpp.2007.15openalex-snapshot
An Effective Strategy for Porting C++ Applications on Cell
inferred← citeshttps://doi.org/10.1109/icpp.2010.21openalex-snapshot
Rearchitecting MapReduce for Heterogeneous Multicore Processors with Explicitly Managed Memories
inferred← citeshttps://doi.org/10.1109/icppw.2011.61openalex-snapshot
CellPilot: A Seamless Communication Solution for Hybrid Cell Clusters
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289226openalex-snapshot
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability
inferred← citeshttps://doi.org/10.1109/icsamos.2010.5642075openalex-snapshot
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
inferred← citeshttps://doi.org/10.1109/infop.2015.7489355openalex-snapshot
Task dependency aware IP core for dynamic scheduling in MPSoC environment
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536190openalex-snapshot
Extended characterization of DMA transfers on the Cell BE processor
inferred← citeshttps://doi.org/10.1109/ipdps.2009.5160939openalex-snapshot
CellFS: Taking the “DMA” out of Cell programming
inferred← citeshttps://doi.org/10.1109/ipdps.2011.120openalex-snapshot
Moving the Code to the Data - Dynamic Code Deployment Using ActiveSpaces
inferred← citeshttps://doi.org/10.1109/ipdps.2011.210openalex-snapshot
Towards an Effective Unified Programming Model for Many-Cores
inferred← citeshttps://doi.org/10.1109/ipdps.2011.23openalex-snapshot
A Study of Speculative Distributed Scheduling on the Cell/B.E.
inferred← citeshttps://doi.org/10.1109/ispa.2012.15openalex-snapshot
Hybrid MPI/StarSs -- A Case Study
inferred← citeshttps://doi.org/10.1109/ispass.2007.363751openalex-snapshot
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications
inferred← citeshttps://doi.org/10.1109/ispass.2011.5762718openalex-snapshot
Trace-driven simulation of multithreaded applications
inferred← citeshttps://doi.org/10.1109/isvlsi.2012.51openalex-snapshot
Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit
inferred← citeshttps://doi.org/10.1109/jproc.2008.917731openalex-snapshot
Scalable Programming Models for Massively Multicore Processors
inferred← citeshttps://doi.org/10.1109/mcse.2010.4openalex-snapshot
Application Acceleration with the Cell Broadband Engine
inferred← citeshttps://doi.org/10.1109/micro.2010.13openalex-snapshot
Task Superscalar: An Out-of-Order Task Pipeline
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00090openalex-snapshot
Sparsepipe: Sparse Inter-operator Dataflow Architecture with Cross-Iteration Reuse
inferred← citeshttps://doi.org/10.1109/mm.2010.76openalex-snapshot
ArchExplorer for Automatic Design Space Exploration
inferred← citeshttps://doi.org/10.1109/noms.2010.5488364openalex-snapshot
Cell BE and Bluetooth applied to Digital TV
inferred← citeshttps://doi.org/10.1109/pacrim.2009.5291299openalex-snapshot
Characterization of single-port and multi-port collective communication operations on the Cell BE processor
inferred← citeshttps://doi.org/10.1109/pact.2009.39openalex-snapshot
Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/pact.2011.7openalex-snapshot
A Unified Scheduler for Recursive and Task Dataflow Parallelism
inferred← citeshttps://doi.org/10.1109/pact.2015.25openalex-snapshot
Scalable Task Scheduling and Synchronization Using Hierarchical Effects
inferred← citeshttps://doi.org/10.1109/pact.2015.26openalex-snapshot
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures
inferred← citeshttps://doi.org/10.1109/pdcat.2012.81openalex-snapshot
Improving Performance of GPU Specific OpenCL Program on CPUs
inferred← citeshttps://doi.org/10.1109/pdp.2010.24openalex-snapshot
Dynamic Task Scheduling and Load Balancing on Cell Processors
inferred← citeshttps://doi.org/10.1109/pdp.2010.42openalex-snapshot
Model Driven Iterative Multi-dimensional Parallelization of Multi-task Programs for the Cell BE: A Genetic Algorithm-Based Approach
inferred← citeshttps://doi.org/10.1109/samos.2011.6045440openalex-snapshot
On the impact of dynamic task scheduling in heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.1109/samos.2011.6045454openalex-snapshot
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms
inferred← citeshttps://doi.org/10.1109/sbac-pad.2007.13openalex-snapshot
Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures
inferred← citeshttps://doi.org/10.1109/sbac-pad.2011.16openalex-snapshot
Parallel Biological Sequence Comparison on Heterogeneous High Performance Computing Platforms with BSP++
inferred← citeshttps://doi.org/10.1109/sbac-pad.2017.21openalex-snapshot
Towards a Deterministic Fine-Grained Task Ordering Using Multi-Versioned Memory
inferred← citeshttps://doi.org/10.1109/sbac-padw.2016.10openalex-snapshot
PY-PITS: A Scalable Python Runtime System for the Computation of Partially Idempotent Tasks
inferred← citeshttps://doi.org/10.1109/sc.2008.5219769openalex-snapshot
Parallel exact inference on the Cell Broadband Engine processor
inferred← citeshttps://doi.org/10.1109/sc.2010.52openalex-snapshot
Strider: Runtime Support for Optimizing Strided Data Accesses on Multi-Cores with Explicitly Managed Memories
inferred← citeshttps://doi.org/10.1109/tpds.2007.70811openalex-snapshot
Efficient Breadth-First Search on the Cell/BE Processor
inferred← citeshttps://doi.org/10.1109/tpds.2010.144openalex-snapshot
Assessing Accelerator-Based HPC Reverse Time Migration
inferred← citeshttps://doi.org/10.1109/tpds.2015.2487346openalex-snapshot
Hardware Implementation on FPGA for Task-Level Parallel Dataflow Execution Engine
inferred← citeshttps://doi.org/10.1145/1463788.1463810openalex-snapshot
OpenMP tasks in IBM XL compilers
inferred← citeshttps://doi.org/10.1145/2884045.2884055openalex-snapshot
Runtime aware architectures
inferred← citeshttps://doi.org/10.1145/3243176.3243200openalex-snapshot
Automatic annotation of tasks in structured code
inferred← citeshttps://doi.org/10.1155/2009/561672openalex-snapshot
CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy
inferred← citeshttps://doi.org/10.1155/2009/741282openalex-snapshot
Available Task-Level Parallelism on the Cell BE
inferred← citeshttps://doi.org/10.1155/2010/540159openalex-snapshot
State-of-the-art in Heterogeneous Computing
inferred← citeshttps://doi.org/10.1155/2010/574728openalex-snapshot
Scheduling Two-Sided Transformations Using Tile Algorithms on Multicore Architectures
inferred← citeshttps://doi.org/10.1201/9781420064872.pt1openalex-snapshot
Synthesizing and Verifying Multicore Parallelism in Categories of Nested Code Graphs
inferred← citeshttps://doi.org/10.1201/b10442-2openalex-snapshot
Multicore Architectures
inferred← citeshttps://doi.org/10.1201/b10442-3openalex-snapshot
◾ Multicore Architectures
inferred← citeshttps://doi.org/10.1201/b10509-18openalex-snapshot
Bibliography
inferred← citeshttps://doi.org/10.14529/jsfi140102openalex-snapshot
Runtime-Aware Architectures: A First Approach
inferred← citeshttps://doi.org/10.1631/jzus.c1100027openalex-snapshot
Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture
inferred← citeshttps://doi.org/10.23919/fruct.2012.8253116openalex-snapshot
Adaptive libraries for multicore architectures with explicitly-managed memory hierarchies
inferred← citeshttps://doi.org/10.3233/ia-160095openalex-snapshot
A constraint programming scheduling solver for the MPOpt programming environment
inferred← citeshttps://doi.org/10.3390/md19080406openalex-snapshot
Marine Sulfated Polysaccharides as Promising Antiviral Agents: A Comprehensive Report and Modeling Study Focusing on SARS CoV-2
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amr.374-377.2078openalex-snapshot
Study on Explicit Memory Management for CBEA Green Computing Architecture
inferred← citeshttps://doi.org/10.4156/ijact.vol1.issue2.2openalex-snapshot
Implementation and Optimization of cGA+LS to solve Capacitated VRP over Cell/B.E.
inferred← citeshttps://doi.org/10.5555/1413370.1413429openalex-snapshot
Parallel exact inference on the cell broadband engine processor
inferred← citeshttps://doi.org/10.5753/wscad.2013.16784openalex-snapshot
Escalonamento Dinâmico Eficiente em Arquiteturas Híbridas
inferred← citeshttps://doi.org/10.5821/dissertation-2117-114007openalex-snapshot
Improving heterogeneous system efficiency : architecture, scheduling, and machine learning
inferred← citeshttps://doi.org/10.5821/dissertation-2117-125844openalex-snapshot
Compiler and runtime based parallelization & optimization for GPUs
inferred← citeshttps://doi.org/10.5821/dissertation-2117-134618openalex-snapshot
Towards resource-aware computing for task-based runtimes and parallel architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-134744openalex-snapshot
Parallel architectures and runtime systems co-design for task-based programming models
inferred← citeshttps://doi.org/10.5821/dissertation-2117-166153openalex-snapshot
Exploiting task-based programming models for resilience
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93345openalex-snapshot
On the programmability of heterogeneous massively-parallel computing systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94569openalex-snapshot
Castell: a heterogeneous cmp architecture scalable to hundreds of processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94598openalex-snapshot
HW/SW mechanisms for instruction fusion, issue and commit in modern u-processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94642openalex-snapshot
Running stream-like programs on heterogeneous multi-core systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95109openalex-snapshot
Performance and power optimizations in chip multiprocessors for throughput-aware computation
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95244openalex-snapshot
Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95396openalex-snapshot
Hardware design of task superscalar architecture
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96004openalex-snapshot
Transparent management of scratchpad memories in shared memory programming models
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.