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NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints

https://doi.org/10.1109/tcad.2008.923063
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/bf02278710openalex-snapshot
A shortest augmenting path algorithm for dense and sparse linear assignment problems
inferredcites →https://doi.org/10.1109/21.293486openalex-snapshot
Efficient local search with search space smoothing: a case study of the traveling salesman problem (TSP)
inferredcites →https://doi.org/10.1109/43.67789openalex-snapshot
GORDIAN: VLSI placement by quadratic programming and slicing optimization
inferredcites →https://doi.org/10.1109/aspdac.2003.1195036openalex-snapshot
Multi-level placement for large-scale mixed-size IC designs
inferredcites →https://doi.org/10.1109/aspdac.2005.1466537openalex-snapshot
Fast floorplanning by look-ahead enabled recursive bipartitioning
inferredcites →https://doi.org/10.1109/iccad.2004.1382607openalex-snapshot
Routability-driven placement and white space allocation
inferredcites →https://doi.org/10.1109/iccad.2004.1382639openalex-snapshot
Unification of partitioning, placement and floorplanning
inferredcites →https://doi.org/10.1109/iccad.2005.1560058openalex-snapshot
Robust mixed size placement under tight white space constraints
inferredcites →https://doi.org/10.1109/iccad.2005.1560188openalex-snapshot
Architecture and details of a high quality, large-scale analytical placer
inferredcites →https://doi.org/10.1109/iccad.2006.320083openalex-snapshot
Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model
inferredcites →https://doi.org/10.1109/tcad.2003.809660openalex-snapshot
Routability-driven white space allocation for fixed-die standard-cell placement
inferredcites →https://doi.org/10.1109/tcad.2005.846366openalex-snapshot
Implementation and extensibility of an analytic placer
inferredcites →https://doi.org/10.1145/1055137.1055177openalex-snapshot
Multilevel generalized force-directed method for circuit placement
inferredcites →https://doi.org/10.1145/1055137.1055178openalex-snapshot
Unified quadratic programming approach for mixed mode placement
inferredcites →https://doi.org/10.1145/1055137.1055186openalex-snapshot
Recursive bisection placement
inferredcites →https://doi.org/10.1145/1055137.1055187openalex-snapshot
APlace
inferredcites →https://doi.org/10.1145/1119772.1119835openalex-snapshot
Multi-level placement for large-scale mixed-size IC designs
inferredcites →https://doi.org/10.1145/1120725.1120838openalex-snapshot
Fast floorplanning by look-ahead enabled recursive bipartitioning
inferredcites →https://doi.org/10.1145/1123008.1123042openalex-snapshot
ISPD 2006 Placement Contest
inferredcites →https://doi.org/10.1145/1123008.1123053openalex-snapshot
Satisfying whitespace requirements in top-down placement
inferredcites →https://doi.org/10.1145/1123008.1123054openalex-snapshot
Dragon2006
inferredcites →https://doi.org/10.1145/1123008.1123055openalex-snapshot
mPL6
inferredcites →https://doi.org/10.1145/1123008.1123056openalex-snapshot
NTUplace2
inferredcites →https://doi.org/10.1145/1123008.1123057openalex-snapshot
A faster implementation of APlace
inferredcites →https://doi.org/10.1145/1233501.1233537openalex-snapshot
Fast and robust quadratic placement combined with an exact linear net model
inferredcites →https://doi.org/10.1145/1233501.1233538openalex-snapshot
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
inferredcites →https://doi.org/10.1145/277044.277119openalex-snapshot
Generic global placement and floorplanning
inferredcites →https://doi.org/10.1145/505388.505400openalex-snapshot
Routability driven white space allocation for fixed-die standard-cell placement
inferredcites →https://doi.org/10.5555/1129601.1129624openalex-snapshot
Robust mixed-size placement under tight white-space constraints

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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RL for Placement and Partitioning
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Matheuristic Local Search for the Placement of Analog Integrated Circuits
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Secure Physical Design
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Placement Optimization for DSAL
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Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization
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Integrated Circuit Floorplanning by Using an Analytical Algorithm
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Fast FPGA Placement Using Analytical Optimization
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Analytical Partitioning: Improvement over FM
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PHetDP: A Placement Algorithm for Heterogeneous FPGAs with Delayed Packing
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A proximal alternating direction method of multipliers for a minimization problem with nonconvex constraints
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Estimating feature importance in circuit network using machine learning
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An augmented Lagrangian method for VLSI global placement
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An analytical timing-driven placer for modern heterogeneous FPGAs
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WHUTPlace: performance-driven analytical placement of analog ICs with common centroid constraints
inferred← citeshttps://doi.org/10.1007/s11432-024-4155-7openalex-snapshot
Large circuit models: opportunities and challenges
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A Nonconvex Nonsmooth PADM for the VLSI Placement Problem
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Introduction
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A Novel Approach for Multilevel Fixed Outline Floorplanning
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An Augmented Lagrangian Optimization Method for VLSI Global Placement
inferred← citeshttps://doi.org/10.1109/reconfig.2013.6732270openalex-snapshot
An effective window based legalization algorithm for FPGA placement
inferred← citeshttps://doi.org/10.1109/tcad.2008.927760openalex-snapshot
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
inferred← citeshttps://doi.org/10.1109/tcad.2011.2163071openalex-snapshot
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs
inferred← citeshttps://doi.org/10.1109/tcad.2011.2165717openalex-snapshot
Pulsed-Latch Aware Placement for Timing-Integrity Optimization
inferred← citeshttps://doi.org/10.1109/tcad.2011.2170567openalex-snapshot
SimPL: An Effective Placement Algorithm
inferred← citeshttps://doi.org/10.1109/tcad.2012.2190289openalex-snapshot
An Analytical Placer for VLSI Standard Cell Placement
inferred← citeshttps://doi.org/10.1109/tcad.2012.2193582openalex-snapshot
Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs
inferred← citeshttps://doi.org/10.1109/tcad.2012.2226584openalex-snapshot
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
inferred← citeshttps://doi.org/10.1109/tcad.2013.2253834openalex-snapshot
BonnPlace Legalization: Minimizing Movement by Iterative Augmentation
inferred← citeshttps://doi.org/10.1109/tcad.2013.2272541openalex-snapshot
Data-Driven Mapping Using Local Patterns
inferred← citeshttps://doi.org/10.1109/tcad.2013.2284010openalex-snapshot
Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics
inferred← citeshttps://doi.org/10.1109/tcad.2014.2351571openalex-snapshot
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint
inferred← citeshttps://doi.org/10.1109/tcad.2014.2360453openalex-snapshot
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs
inferred← citeshttps://doi.org/10.1109/tcad.2014.2376988openalex-snapshot
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization
inferred← citeshttps://doi.org/10.1109/tcad.2014.2385754openalex-snapshot
TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global Placement
inferred← citeshttps://doi.org/10.1109/tcad.2015.2391263openalex-snapshot
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2015.2394383openalex-snapshot
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2015.2394484openalex-snapshot
Nonsmooth Optimization Method for VLSI Global Placement
inferred← citeshttps://doi.org/10.1109/tcad.2015.2501293openalex-snapshot
Layout-Dependent Effects-Aware Analytical Analog Placement
inferred← citeshttps://doi.org/10.1109/tcad.2017.2695900openalex-snapshot
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs
inferred← citeshttps://doi.org/10.1109/tcad.2017.2712665openalex-snapshot
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2017.2729349openalex-snapshot
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing
inferred← citeshttps://doi.org/10.1109/tcad.2018.2859220openalex-snapshot
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
inferred← citeshttps://doi.org/10.1109/tcad.2018.2877017openalex-snapshot
A New Paradigm for FPGA Placement Without Explicit Packing
inferred← citeshttps://doi.org/10.1109/tcad.2019.2917896openalex-snapshot
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design
inferred← citeshttps://doi.org/10.1109/tcad.2020.2968892openalex-snapshot
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
inferred← citeshttps://doi.org/10.1109/tcad.2020.2971531openalex-snapshot
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2020.3002570openalex-snapshot
Analytical Placement Considering the Electron-Beam Fogging Effect
inferred← citeshttps://doi.org/10.1109/tcad.2020.3003843openalex-snapshot
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
inferred← citeshttps://doi.org/10.1109/tcad.2020.3025075openalex-snapshot
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale
inferred← citeshttps://doi.org/10.1109/tcad.2020.3032619openalex-snapshot
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2021.3053223openalex-snapshot
Pin-Accessible Legalization for Mixed-Cell-Height Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2021.3120070openalex-snapshot
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness
inferred← citeshttps://doi.org/10.1109/tcad.2021.3133855openalex-snapshot
Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2022.3155066openalex-snapshot
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects
inferred← citeshttps://doi.org/10.1109/tcad.2022.3190234openalex-snapshot
Interactive Analog Layout Editing With Instant Placement and Routing Legalization
inferred← citeshttps://doi.org/10.1109/tcad.2022.3213609openalex-snapshot
PeF: Poisson’s Equation-Based Large-Scale Fixed-Outline Floorplanning
inferred← citeshttps://doi.org/10.1109/tcad.2023.3320628openalex-snapshot
Pplace-MS: Methodologically Faster Poisson’s Equation-Based Mixed-Size Global Placement
inferred← citeshttps://doi.org/10.1109/tcad.2023.3329774openalex-snapshot
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints
inferred← citeshttps://doi.org/10.1109/tcad.2023.3346291openalex-snapshot
Xplace: An Extremely Fast and Extensible Placement Framework
inferred← citeshttps://doi.org/10.1109/tcad.2023.3347293openalex-snapshot
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration
inferred← citeshttps://doi.org/10.1109/tcad.2024.3444716openalex-snapshot
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros
inferred← citeshttps://doi.org/10.1109/tcad.2025.3531776openalex-snapshot
IncreMacro: Incremental Macro Placement Refinement
inferred← citeshttps://doi.org/10.1109/tcad.2025.3580346openalex-snapshot
Rotation Mutation-Driven Evolutionary Algorithm for Efficient Macro Placement
inferred← citeshttps://doi.org/10.1109/tcad.2025.3620248openalex-snapshot
LightPlace: A Lightweight and Connectivity-Aware Macro Placement Framework for Mixed-Size 3-D ICs
inferred← citeshttps://doi.org/10.1109/tcad.2025.3635566openalex-snapshot
RollPlace: Improving Macro Placement via Monte Carlo Rollout Search
inferred← citeshttps://doi.org/10.1109/tcad.2026.3652945openalex-snapshot
EvoPlace: Evolution of Optimization Algorithms for Global Placement via Large Language Models
inferred← citeshttps://doi.org/10.1109/tcsii.2023.3306036openalex-snapshot
An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting
inferred← citeshttps://doi.org/10.1109/tetci.2023.3336928openalex-snapshot
MS-CLS: An Effective Partitioning and Placement Metaheuristic for Wafer-Scale Physics Modeling
inferred← citeshttps://doi.org/10.1109/tvlsi.2010.2047876openalex-snapshot
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2214408openalex-snapshot
Fast and Effective Placement Refinement for Routability
inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2572224openalex-snapshot
Lithography Defect Probability and Its Application to Physical Design Optimization
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2867833openalex-snapshot
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3057921openalex-snapshot
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3062669openalex-snapshot
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation
inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3100343openalex-snapshot
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC
inferred← citeshttps://doi.org/10.1109/tvlsi.2022.3201946openalex-snapshot
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3309595openalex-snapshot
A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs
inferred← citeshttps://doi.org/10.1109/vlsi-soc54400.2022.9939588openalex-snapshot
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography
inferred← citeshttps://doi.org/10.1109/vlsid.2015.77openalex-snapshot
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits
inferred← citeshttps://doi.org/10.1109/vlsid2022.2022.00037openalex-snapshot
Stitch-avoiding Global Routing for Multiple E-Beam Lithography
inferred← citeshttps://doi.org/10.1109/vlsid49098.2020.00031openalex-snapshot
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer
inferred← citeshttps://doi.org/10.1142/s0218126614500169openalex-snapshot
A PLACEMENT FLOW FOR VERY LARGE-SCALE MIXED-SIZE CIRCUIT PLACEMENT
inferred← citeshttps://doi.org/10.1142/s0218126618501220openalex-snapshot
Kapees3: A High-Quality VLSI Placement Tool Using Nesterov’s Method for Density Penalty
inferred← citeshttps://doi.org/10.1145/1278480.1278598openalex-snapshot
MP-trees
inferred← citeshttps://doi.org/10.1145/1687399.1687465openalex-snapshot
CROP
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