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Timing Recovery in Digital Synchronous Data Receivers

https://doi.org/10.1109/tcom.1976.1093326

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Statistics of Regenerative Digital Transmission

inferredcites →https://doi.org/10.1002/j.1538-7305.1967.tb04235.xopenalex-snapshot

Timing Recovery for Synchronous Binary Data Transmission

inferredcites →https://doi.org/10.1002/j.1538-7305.1971.tb02574.xopenalex-snapshot

Timing Recovery in PAM Systems

inferredcites →https://doi.org/10.1016/b978-1-4832-2939-3.50008-9openalex-snapshot

Stochastic Approximation: A Recursive Method for Solving Regression Problems1 1This work was supported in part by the Joint Services Electronics Program (U.S. Army, U.S. Navy and U.S. Air Force under Grant No. AF-AFOSR-139-65.

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A Self Bit Synchronizer Matched to the Signal Shape

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Generalization of a Techinque for Binary Data Communication

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Decision-Directed Digital Adaptive Equalization Technique for High-Speed Data Transmission

inferredcites →https://doi.org/10.1109/tcom.1971.1090639openalex-snapshot

Simultaneous Adaptive Estimation and Decision Algorithm for Carrier Modulated Data Transmission Systems

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A New Digital Coherent Demodulator

inferredcites →https://doi.org/10.1109/tcom.1974.1092318openalex-snapshot

Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme

inferredcites →https://doi.org/10.1214/aoms/1177729586openalex-snapshot

A Stochastic Approximation Method

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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A simple diagram for data transmission using Manchester code

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An Improved Update Rate Baud Rate CDR for Integrating Human Body Communication Receiver

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A symbol timing recovery algorithm of M-PSK signals for burst modem applications with small packet size

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Two new decision directed M-PSK timing error detectors

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A Novel Technique for Fast Clock Phase and Frequency Offset Simulation in Digital Communication Systems

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A universal synchronization algorithm of joint timing — Carrier in all digital receivers

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Flag Based All Digital Timing Recovery

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Two-dimensional signal processing for timing recovery using PLLs for storage channels

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A fully integrated digital demodulation and forward error correction IC for digital satellite television

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Integrated circuits for data transmission over twisted-pair channels

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A VLSI low power solution for mobile satellite radio receivers

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A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 μm CMOS technology

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A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization

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ADC-based serial I/O receivers

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Design metrics for blind ADC-based wireline receivers

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A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE

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A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited)

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Low-Complexity and Multiplier-Free Baud-Rate Timing Phase Error Detector for High-Speed Optical IM/DD Systems

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Signal processing for high-density digital magnetic recording

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A new architecture for coherent M-PSK receivers

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A soft maximum likelihood technique for time delay recovery

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Effects of timing information for a magnetic recording channel in the presence of non-linearities

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An Improved Early-Late Gate Timing Synchronization Loop for Low SNR Environment

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Coverage Analysis of Drone-Assisted Backscatter Communication for IoT Sensor Network

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An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector

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An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector

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Clock and carrier recovery for coherent receivers

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Performance and DSP complexity evaluation of a 112-Gbit/s PAM-4 transceiver employing a 25-GHz TOSA and ROSA

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A 0.07-pJ/bdB 32-Gb/s Receiver with Pattern-Based Baud-Rate CDR and DFE Adaptation Using 2UI Integrator without Data-Level Reference

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ISDN U transceiver algorithm, development system, and performance

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VLSI implementation of synchronization algorithms in a 100 Mbit/s digital receiver

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Carrier-independent NDA symbol synchronization for M-PSK, operating at only one sample per symbol

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Timing recovery for adaptive decision feedback equalization of the magnetic storage channel

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Synchronization technique for optical OOK receivers

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Filter coefficient interpolated timing recovery in sampled coherent PSK receivers

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Analog timing recovery architectures for PRML detectors

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A new symbol synchronizer with reduced timing jitter for QAM systems

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Convergence analysis of a PLL for a digital recording channel with an adaptive partial response equalizer

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Blind synchronization techniques for telephony over HFC networks using M-QAM

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Symbol timing recovery using digital spectral line method for 16-CAP VDSL system

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A novel timing recovery scheme for FDTS/DF detector

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Equalizer-based symbol-rate timing recovery for digital subscriber line systems

showing the first 200 of 610

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