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Efficient Hardware Architectures for Deep Convolutional Neural Network

https://doi.org/10.1109/tcsi.2017.2767204
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Outgoing claims: the papers this work cites, builds on, or argues with.

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inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
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inferredcites →https://doi.org/10.1109/lascas.2012.6180303openalex-snapshot
Low power 3–2 and 4–2 adder compressors implemented using ASTRAN
inferredcites →https://doi.org/10.1109/micro.2014.58openalex-snapshot
DaDianNao: A Machine-Learning Supercomputer
inferredcites →https://doi.org/10.1109/micro.2016.7783725openalex-snapshot
Fused-layer CNN accelerators
inferredcites →https://doi.org/10.1109/pdp.2010.43openalex-snapshot
Performance and Scalability of GPU-Based Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/taslp.2014.2339736openalex-snapshot
Convolutional Neural Networks for Speech Recognition
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Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution
inferredcites →https://doi.org/10.1109/wacv.2016.7477450openalex-snapshot
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inferredcites →https://doi.org/10.1109/wcsp.2016.7752720openalex-snapshot
Intra-layer nonuniform quantization of convolutional neural network
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DianNao
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PuDianNao
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PuDianNao
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inferredcites →https://doi.org/10.1145/2966986.2967011openalex-snapshot
Caffeine
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EIE
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ImageNet classification with deep convolutional neural networks
inferredcites →https://doi.org/10.48550/arxiv.1312.6229openalex-snapshot
OverFeat: Integrated Recognition, Localization and Detection using Convolutional Networks
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Very Deep Convolutional Networks for Large-Scale Image Recognition
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BinaryConnect: Training Deep Neural Networks with binary weights during propagations
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Fixed Point Quantization of Deep Convolutional Networks
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Deep Residual Learning for Image Recognition

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Low Complexity Parallel FIR Filter Circuit Design by Exploiting Signal Correlation in Multimedia Applications
inferred← citeshttps://doi.org/10.1142/s0218126622502899openalex-snapshot
RNA: A Flexible and Efficient Accelerator Based on Dynamically Reconfigurable Computing for Multiple Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1142/s0218126623500755openalex-snapshot
A Resource Efficient CNN Accelerator for Sensor Signal Processing Based on FPGA
inferred← citeshttps://doi.org/10.1145/3338852.3339840openalex-snapshot
A FPGA parameterizable multi-layer architecture for CNNs
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3820413/v1openalex-snapshot
Optimizing FPGA-Based Target Detection: A Hybrid Winograd-GEMM Accelerator with Enhanced Resource Efficiency and Throughput
inferred← citeshttps://doi.org/10.22214/ijraset.2022.46913openalex-snapshot
Design of Area-Power Efficient Parallel Fir Filter with Mux Based Full Adder
inferred← citeshttps://doi.org/10.32604/cmc.2020.012380openalex-snapshot
A Dynamically Reconfigurable Accelerator Design Using a Sparse-Winograd Decomposition Algorithm for CNNs
inferred← citeshttps://doi.org/10.32604/cmc.2023.045948openalex-snapshot
FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy
inferred← citeshttps://doi.org/10.3389/fenvs.2024.1291327openalex-snapshot
Predicting groundwater level using traditional and deep machine learning algorithms
inferred← citeshttps://doi.org/10.3390/agriculture12111849openalex-snapshot
FPGA Implementation of a Convolutional Neural Network and Its Application for Pollen Detection upon Entrance to the Beehive
inferred← citeshttps://doi.org/10.3390/ai6010008openalex-snapshot
Accelerating Deep Learning-Based Morphological Biometric Recognition with Field-Programmable Gate Arrays
inferred← citeshttps://doi.org/10.3390/app8122670openalex-snapshot
Dark Spot Detection in SAR Images of Oil Spill Using Segnet
inferred← citeshttps://doi.org/10.3390/electronics10232889openalex-snapshot
A Real-Time FPGA Accelerator Based on Winograd Algorithm for Underwater Object Detection
inferred← citeshttps://doi.org/10.3390/electronics12244943openalex-snapshot
WRA-MF: A Bit-Level Convolutional-Weight-Decomposition Approach to Improve Parallel Computing Efficiency for Winograd-Based CNN Acceleration
inferred← citeshttps://doi.org/10.3390/electronics8020143openalex-snapshot
An Accelerator Architecture of Changeable-Dimension Matrix Computing Method for SVM
inferred← citeshttps://doi.org/10.3390/electronics8111321openalex-snapshot
Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning
inferred← citeshttps://doi.org/10.3390/electronics9091526openalex-snapshot
A Neural Network Decomposition Algorithm for Mapping on Crossbar-Based Computing Systems
inferred← citeshttps://doi.org/10.3390/electronics9111823openalex-snapshot
mNet2FPGA: A Design Flow for Mapping a Fixed-Point CNN to Zynq SoC FPGA
inferred← citeshttps://doi.org/10.3390/s20195558openalex-snapshot
An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs
inferred← citeshttps://doi.org/10.3390/s22155874openalex-snapshot
Heuristic Method for Minimizing Model Size of CNN by Combining Multiple Pruning Techniques
inferred← citeshttps://doi.org/10.3390/s23042045openalex-snapshot
A Low-Power Hardware Architecture for Real-Time CNN Computing
inferred← citeshttps://doi.org/10.34133/plantphenomics.0234openalex-snapshot
Deep Learning Methods Using Imagery from a Smartphone for Recognizing Sorghum Panicles and Counting Grains at a Plant Level
inferred← citeshttps://doi.org/10.36227/techrxiv.22728788openalex-snapshot
S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications
inferred← citeshttps://doi.org/10.48084/etasr.6761openalex-snapshot
Hardware Acceleration for Object Detection using YOLOv5 Deep Learning Algorithm on Xilinx Zynq FPGA Platform
inferred← citeshttps://doi.org/10.7256/2454-0714.2024.1.69919openalex-snapshot
Research and development of algorithms for the formation of an effective ensemble of convolutional neural networks for image classification
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