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Design of a Ternary Memory Cell Using CNTFETs

https://doi.org/10.1109/tnano.2012.2211614

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Impact of Process Variation on Nanowire and Nanotube Device Performance

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Realization of quaternary logic circuits by n-channel MOS devices

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Static-noise margin analysis of MOS SRAM cells

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Device Model for Ballistic CNFETs Using the First Conducting Band

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Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics

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Design of Ternary COS/MOS Memory and Sequential Circuits

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The Prospects for Multivalued Logic: A Technology and Applications View

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A Survey of Multivalued Memories

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Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity

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Impact of a Process Variation on Nanowire and Nanotube Device Performance

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A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

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A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

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Carbon-Nanotube-Based Voltage-Mode Multiple-Valued Logic Design

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High-Performance Carbon Nanotube Field-Effect Transistor With Tunable Polarities

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CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits

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An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Noise-Immune Digital Circuit Design Based on Probabilistic Models

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Design of High-Speed GNRFET Based Ternary Logic Circuits

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An Operational Transconductance Amplifiers Based Sinusoidal Oscillator Using CNTFETs

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Performance Analysis of CNFET Based 6T SRAM

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Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)

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Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs

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Multiple negative differential resistance devices with ultra-high peak-to-valley current ratio for practical multi-valued logic and memory applications

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Effect of Dielectric Variations on Performance of Carbon Nanotube Field Effect Transistor Based Basic Logic Gates

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