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NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps
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Outgoing claims: the papers this work cites, builds on, or argues with.
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XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
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Evaluation of Pooling Operations in Convolutional Architectures for Object Recognition
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The perceptron: A probabilistic model for information storage and organization in the brain.
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Digital selection and analogue amplification coexist in a cortex-inspired silicon circuit
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Histograms of Oriented Gradients for Human Detection
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Deep Residual Learning for Image Recognition
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EIE: Efficient Inference Engine on Compressed Deep Neural Network
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Live demonstration: Convolutional neural network driven by dynamic vision sensor playing RoShamBo
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14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
inferredcites →https://doi.org/10.1109/isscc.2016.7418008openalex-snapshot
14.6 A 1.42TOPS/W deep convolutional neural network recognition processor for intelligent IoE systems
inferredcites →https://doi.org/10.1109/isscc.2017.7870350openalex-snapshot
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks
inferredcites →https://doi.org/10.1109/isscc.2017.7870353openalex-snapshot
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI
inferredcites →https://doi.org/10.1109/isscc.2018.8310262openalex-snapshot
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision
inferredcites →https://doi.org/10.1109/jssc.2014.2342715openalex-snapshot
A 240 × 180 130 dB 3 µs Latency Global Shutter Spatiotemporal Vision Sensor
inferredcites →https://doi.org/10.1109/jssc.2016.2616357openalex-snapshot
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/micro.2016.7783723openalex-snapshot
Cambricon-X: An accelerator for sparse neural networks
inferredcites →https://doi.org/10.1109/mwscas.2012.6292202openalex-snapshot
NeuFlow: Dataflow vision processing system-on-a-chip
inferredcites →https://doi.org/10.1109/vlsic.2016.7573525openalex-snapshot
A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
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ImageNet classification with deep convolutional neural networks
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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In-Datacenter Performance Analysis of a Tensor Processing Unit
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inferredcites →https://doi.org/10.3389/fnins.2015.00222openalex-snapshot
Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms
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Very Deep Convolutional Networks for Large-Scale Image Recognition
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Fixed Point Quantization of Deep Convolutional Networks
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Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations
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Delta Networks for Optimized Recurrent Network Computation
inferredcites →https://doi.org/10.48550/arxiv.1709.01134openalex-snapshot
WRPN: Wide Reduced-Precision Networks
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ADaPTION: Toolbox and Benchmark for Training Convolutional Neural Networks with Reduced Numerical Precision Weights and Activation
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DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS
inferredcites →https://doi.org/10.7873/date.2015.0408openalex-snapshot
DRAM or no-DRAM? Exploring Linear Solver Architectures for Image Domain Warping in 28 nm CMOS
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Incremental Learning Meets Reduced Precision Networks
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Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180844openalex-snapshot
A Convolutional Neural Network Accelerator Architecture with Fine-Granular Mixed Precision Configurability
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180983openalex-snapshot
Lessons Learned the Hard Way
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181259openalex-snapshot
Live Demonstration: CNN Edge Computing for Mobile Robot Navigation
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937651openalex-snapshot
A Fast Compressed Hardware Architecture for Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401133openalex-snapshot
Transform-Based Feature Map Compression for CNN Inference
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043407openalex-snapshot
An FPGA Processor Combining Point Cloud and SNN for DVS-based ADAS Application
inferred← citeshttps://doi.org/10.1109/ivs.2019.8814001openalex-snapshot
CNN-based Object Detection on Low Precision Hardware: Racing Car Case Study
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2905654openalex-snapshot
Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2934929openalex-snapshot
Tightly Coupled Machine Learning Coprocessor Architecture With Analog In-Memory Computing for Instruction-Level Acceleration
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2950093openalex-snapshot
EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2951121openalex-snapshot
Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity
inferred← citeshttps://doi.org/10.1109/jetcas.2019.2952137openalex-snapshot
Memory-Reduced Network Stacking for Edge-Level CNN Architecture With Structured Weight Pruning
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3031040openalex-snapshot
Digital Multiplier-Less Spiking Neural Network Architecture of Reinforcement Learning in a Context-Dependent Task
inferred← citeshttps://doi.org/10.1109/jetcas.2020.3033155openalex-snapshot
Siamese Networks for Few-Shot Learning on Edge Embedded Devices
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3116611openalex-snapshot
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3120417openalex-snapshot
An Overview of Sparsity Exploitation in CNNs for On-Device Intelligence With Software-Hardware Cross-Layer Optimizations
inferred← citeshttps://doi.org/10.1109/jetcas.2021.3129415openalex-snapshot
A Survey on the Optimization of Neural Network Accelerators for Micro-AI On-Device Inference
inferred← citeshttps://doi.org/10.1109/jetcas.2024.3445829openalex-snapshot
Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific, and Quantum Computing Systems—Overview, Challenges, and Opportunities
inferred← citeshttps://doi.org/10.1109/jiot.2020.2990215openalex-snapshot
AWARE-CNN: Automated Workflow for Application-Aware Real-Time Edge Acceleration of CNNs
inferred← citeshttps://doi.org/10.1109/jiot.2022.3209401openalex-snapshot
Multiobjective End-to-End Design Space Exploration of Parameterized DNN Accelerators
inferred← citeshttps://doi.org/10.1109/jiot.2023.3306435openalex-snapshot
Sagitta: An Energy-Efficient Sparse 3D-CNN Accelerator for Real-Time 3-D Understanding
inferred← citeshttps://doi.org/10.1109/jiot.2023.3314820openalex-snapshot
SNPF: Sensitiveness-Based Network Pruning Framework for Efficient Edge Computing
inferred← citeshttps://doi.org/10.1109/jiot.2024.3386832openalex-snapshot
RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge
inferred← citeshttps://doi.org/10.1109/jlt.2019.2903474openalex-snapshot
Machine Learning With Neuromorphic Photonics
inferred← citeshttps://doi.org/10.1109/jproc.2020.2976475openalex-snapshot
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
inferred← citeshttps://doi.org/10.1109/jproc.2021.3098483openalex-snapshot
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights
inferred← citeshttps://doi.org/10.1109/jproc.2022.3226481openalex-snapshot
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review
inferred← citeshttps://doi.org/10.1109/jsen.2022.3189679openalex-snapshot
A Bio-Inspired Hierarchical Spiking Neural Network With Reward-Modulated STDP Learning Rule for AER Object Recognition
inferred← citeshttps://doi.org/10.1109/jssc.2020.3029235openalex-snapshot
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access
inferred← citeshttps://doi.org/10.1109/jssc.2025.3604814openalex-snapshot
ROZK: An Energy-Efficient DNN Accelerator Based on Reconfigurable NoC and Local Zero-Skipping
inferred← citeshttps://doi.org/10.1109/jstars.2021.3119988openalex-snapshot
Proportion Estimation for Urban Mixed Scenes Based on Nonnegative Matrix Factorization for High-Spatial Resolution Remote Sensing Images
inferred← citeshttps://doi.org/10.1109/meco.2019.8760160openalex-snapshot
Age & Gender Classifier for Edge Computing
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00066openalex-snapshot
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture
inferred← citeshttps://doi.org/10.1109/mpcon66082.2025.11256597openalex-snapshot
VLSI Architecture Implementation of Selective Level Skip Discrete Wavelet Transform for Efficient Lossy Image Compression
inferred← citeshttps://doi.org/10.1109/msp.2019.2928376openalex-snapshot
The Importance of Space and Time for Signal Processing in Neuromorphic Agents: The Challenge of Developing Low-Power, Autonomous Agents That Interact With the Environment
inferred← citeshttps://doi.org/10.1109/mwscas54063.2022.9859319openalex-snapshot
Compressed Sparse Kernel: Optimization of Pruning for Customized CNNs on FPGAs
inferred← citeshttps://doi.org/10.1109/nano.2018.8626313openalex-snapshot
Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator
inferred← citeshttps://doi.org/10.1109/nnice58320.2023.10105734openalex-snapshot
A Flexible and Low-Resource CNN Accelerator on FPGA for Edge Computing
inferred← citeshttps://doi.org/10.1109/norcas58970.2023.10305446openalex-snapshot
FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic Scintillator
inferred← citeshttps://doi.org/10.1109/ojcas.2020.3037758openalex-snapshot
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
inferred← citeshttps://doi.org/10.1109/ojcas.2020.3041685openalex-snapshot
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/ojcas.2023.3245061openalex-snapshot
An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness
inferred← citeshttps://doi.org/10.1109/raics61201.2024.10690128openalex-snapshot
Design of a Computationally Efficient 1-D Convolutional Neural Network Hardware for ECG Classification in Portable Devices
inferred← citeshttps://doi.org/10.1109/ro-man60168.2024.10731344openalex-snapshot
A Rapid and Robust Tendon-Driven Robotic Hand for Human-Robot Interactions Playing Rock-Paper-Scissors
inferred← citeshttps://doi.org/10.1109/sensors43011.2019.8956592openalex-snapshot
Audio classification systems using deep neural networks and an event-driven auditory sensor
inferred← citeshttps://doi.org/10.1109/sips50750.2020.9195227openalex-snapshot
Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems
inferred← citeshttps://doi.org/10.1109/tbcas.2018.2880012openalex-snapshot
Neuromorphic LIF Row-by-Row Multi-convolution Processor for FPGA
inferred← citeshttps://doi.org/10.1109/tc.2022.3184272openalex-snapshot
DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs
inferred← citeshttps://doi.org/10.1109/tc.2022.3212642openalex-snapshot
Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition with Hierarchical Tucker Tensor Decomposition
inferred← citeshttps://doi.org/10.1109/tcad.2018.2857019openalex-snapshot
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference
inferred← citeshttps://doi.org/10.1109/tcad.2021.3082107openalex-snapshot
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks
inferred← citeshttps://doi.org/10.1109/tcad.2022.3183561openalex-snapshot
A Speculative Computation Approach for Energy-Efficient Deep Neural Network
inferred← citeshttps://doi.org/10.1109/tcad.2022.3232467openalex-snapshot
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching
inferred← citeshttps://doi.org/10.1109/tcasai.2024.3502573openalex-snapshot
BioPI: An Energy Efficient and Low-Latency Neuromorphic Pipelined System With Joint Design Optimizations of Sensor-Algorithm-Processor for Wearable Healthcare
inferred← citeshttps://doi.org/10.1109/tcds.2023.3334010openalex-snapshot
LC-TTFS: Toward Lossless Network Conversion for Spiking Neural Networks With TTFS Coding
inferred← citeshttps://doi.org/10.1109/tce.2025.3582301openalex-snapshot
A Delta Recurrent Neural Network Over TinyML Framework for Arithmetic Coding on the Edge
inferred← citeshttps://doi.org/10.1109/tcsi.2020.3012576openalex-snapshot
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node
inferred← citeshttps://doi.org/10.1109/tcsi.2021.3055281openalex-snapshot
Memory Access Optimization for On-Chip Transfer Learning
inferred← citeshttps://doi.org/10.1109/tcsi.2022.3194636openalex-snapshot
An Efficient Unstructured Sparse Convolutional Neural Network Accelerator for Wearable ECG Classification Device
inferred← citeshttps://doi.org/10.1109/tcsi.2022.3228860openalex-snapshot
Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3337283openalex-snapshot
ASC: Adaptive Scale Feature Map Compression for Deep Neural Network
inferred← citeshttps://doi.org/10.1109/tcsii.2018.2865896openalex-snapshot
A CNN Accelerator on FPGA Using Depthwise Separable Convolution
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3150980openalex-snapshot
TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization
inferred← citeshttps://doi.org/10.1109/tcsii.2022.3213847openalex-snapshot
Area Efficient Compression for Floating-Point Feature Maps in Convolutional Neural Network Accelerators
inferred← citeshttps://doi.org/10.1109/tcsii.2023.3239044openalex-snapshot
An Ultra-Low Power TinyML System for Real-Time Visual Processing at Edge
inferred← citeshttps://doi.org/10.1109/tcsii.2025.3563062openalex-snapshot
A 40 TOPS Single-Chip Accelerator Enabling Low-Latency Inference for Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/tcss.2021.3059318openalex-snapshot
Collaborative Edge Computing With FPGA-Based CNN Accelerators for Energy-Efficient and Time-Aware Face Tracking System
inferred← citeshttps://doi.org/10.1109/tcsvt.2019.2903421openalex-snapshot
CBinfer: Exploiting Frame-to-Frame Locality for Faster Convolutional Network Inference on Video Streams
inferred← citeshttps://doi.org/10.1109/tcsvt.2022.3145024openalex-snapshot
A 1Mb Mixed-Precision Quantized Encoder for Image Classification and Patch-Based Compression
inferred← citeshttps://doi.org/10.1109/tcsvt.2023.3274964openalex-snapshot
CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow
inferred← citeshttps://doi.org/10.1109/tii.2024.3438284openalex-snapshot
FPGA Adaptive Neural Network Quantization for Adversarial Image Attack Defense
inferred← citeshttps://doi.org/10.1109/tla.2020.9082927openalex-snapshot
Review of prominent strategies for mapping CNNs onto embedded systems
inferred← citeshttps://doi.org/10.1109/tnnls.2020.2970827openalex-snapshot
2019 Index IEEE Transactions on Neural Networks and Learning Systems Vol. 30
inferred← citeshttps://doi.org/10.1109/tnnls.2020.3029613openalex-snapshot
A Lightweight Encoder–Decoder Path for Deep Residual Networks
inferred← citeshttps://doi.org/10.1109/tnnls.2020.3046452openalex-snapshot
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
inferred← citeshttps://doi.org/10.1109/tnnls.2021.3109064openalex-snapshot
Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization
inferred← citeshttps://doi.org/10.1109/tnnls.2021.3116302openalex-snapshot
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point
inferred← citeshttps://doi.org/10.1109/tnnls.2022.3180209openalex-snapshot
Spartus: A 9.4 TOp/s FPGA-Based LSTM Accelerator Exploiting Spatio-Temporal Sparsity
inferred← citeshttps://doi.org/10.1109/tpami.2019.2963386openalex-snapshot
High Speed and High Dynamic Range Video with an Event Camera
inferred← citeshttps://doi.org/10.1109/tpami.2020.3008413openalex-snapshot
Event-Based Vision: A Survey
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