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High-Throughput Multi-Core LDPC Decoders Based on x86 Processor

https://doi.org/10.1109/tpds.2015.2435787
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/s10470-012-9895-7openalex-snapshot
Efficient GPU and CPU-based LDPC decoders for long codewords
inferredcites →https://doi.org/10.1007/s11227-011-0587-3openalex-snapshot
Tridimensional block multiword LDPC decoding on GPUs
inferredcites →https://doi.org/10.1007/s11265-010-0547-9openalex-snapshot
Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU
inferredcites →https://doi.org/10.1007/s11265-011-0604-zopenalex-snapshot
Architecture and Finite Precision Optimization for Layered LDPC Decoders
inferredcites →https://doi.org/10.1007/s11390-009-9266-8openalex-snapshot
Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach
inferredcites →https://doi.org/10.1049/el.2011.0201openalex-snapshot
GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection
inferredcites →https://doi.org/10.1049/el:19970362openalex-snapshot
Near Shannon limit performance of low density paritycheck codes
inferredcites →https://doi.org/10.1049/el:20081927openalex-snapshot
High coded data rate and multicodeword WiMAX LDPC decoding on Cell/BE
inferredcites →https://doi.org/10.1109/26.768759openalex-snapshot
Reduced complexity iterative decoding of low-density parity check codes based on belief propagation
inferredcites →https://doi.org/10.1109/26.990903openalex-snapshot
Near optimum universal belief propagation based decoding of low-density parity check codes
inferredcites →https://doi.org/10.1109/acssc.2008.5074385openalex-snapshot
A parallel decoding algorithm of LDPC codes using CUDA
inferredcites →https://doi.org/10.1109/acssc.2011.6190388openalex-snapshot
GPU accelerated scalable parallel decoding of LDPC codes
inferredcites →https://doi.org/10.1109/cmc.2011.117openalex-snapshot
High Performance LDPC Decoder on CELL BE for WiMAX System
inferredcites →https://doi.org/10.1109/globalsip.2013.6737137openalex-snapshot
High throughput low latency LDPC decoding on GPU for SDR systems
inferredcites →https://doi.org/10.1109/globalsip.2013.6737142openalex-snapshot
Performance evaluation of LDPC decoding on a general purpose mobile CPU
inferredcites →https://doi.org/10.1109/icc.2012.6363991openalex-snapshot
Parallel LDPC decoder implementation on GPU based on unbalanced memory coalescing
inferredcites →https://doi.org/10.1109/icct.2013.6820375openalex-snapshot
Implementation of IEEE 802.11n LDPC codes based on general purpose processors
inferredcites →https://doi.org/10.1109/iscas.2012.6271839openalex-snapshot
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost
inferredcites →https://doi.org/10.1109/jstars.2011.2142295openalex-snapshot
Accelerating Regular LDPC Code Decoders on GPUs
inferredcites →https://doi.org/10.1109/lcomm.2014.010214.132406openalex-snapshot
High Throughput LDPC Decoder on GPU
inferredcites →https://doi.org/10.1109/les.2014.2311317openalex-snapshot
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices
inferredcites →https://doi.org/10.1109/msp.2012.2192212openalex-snapshot
Portable LDPC Decoding on Multicores Using OpenCL [Applications Corner]
inferredcites →https://doi.org/10.1109/sasp.2011.5941084openalex-snapshot
A massively parallel implementation of QC-LDPC decoder on GPU
inferredcites →https://doi.org/10.1109/sips.2004.1363033openalex-snapshot
A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes
inferredcites →https://doi.org/10.1109/sips.2009.5336268openalex-snapshot
Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unit
inferredcites →https://doi.org/10.1109/sips.2010.5624781openalex-snapshot
Design and FPGA prototyping of a bit-interleaved coded modulation receiver for the DVB-T2 standard
inferredcites →https://doi.org/10.1109/sips.2010.5624816openalex-snapshot
Architecture and finite precision optimization for layered LDPC decoders
inferredcites →https://doi.org/10.1109/spawc.2013.6612145openalex-snapshot
A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs
inferredcites →https://doi.org/10.1109/tcomm.2007.908517openalex-snapshot
Generic Description and Synthesis of LDPC Decoders
inferredcites →https://doi.org/10.1109/tit.1962.1057683openalex-snapshot
Low-density parity-check codes
inferredcites →https://doi.org/10.1109/tpds.2010.66openalex-snapshot
Massively LDPC Decoding on Multicore Architectures
inferredcites →https://doi.org/10.1109/tsp.2014.2311964openalex-snapshot
A Flexible NISC-Based LDPC Decoder
inferredcites →https://doi.org/10.1109/wcncw.2013.6533323openalex-snapshot
A high throughput LDPC decoder in CMMB based on virtual radio
inferredcites →https://doi.org/10.1117/12.862716openalex-snapshot
High-throughput GPU-based LDPC decoding
inferredcites →https://doi.org/10.1145/2538668openalex-snapshot
GPU-like on-chip system for decoding LDPC codes
inferredcites →https://doi.org/10.5860/choice.46-0930openalex-snapshot
Using OpenMP: portable shared memory parallel programming

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Efficient GPU‐based implementation for decoding non‐binary LDPC codes with layered and flooding schedules
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StreamPU: A DSEL for high throughput and low latency software‐defined radio on multicore CPUs
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High-Performance Gallager-E Decoders for Hard Input LDPC Decoding on Multi-core Devices
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High-Throughput Implementation of QC-LDPC on RaPro Prototyping Platform
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RETRACTED ARTICLE: High performance reconciliation for practical quantum key distribution systems
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High-throughput and low-cost LDPC reconciliation for quantum key distribution
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Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding
inferred← citeshttps://doi.org/10.1007/s11265-019-01447-8openalex-snapshot
High-Throughput FFT-SPA Decoder Implementation for Non-Binary LDPC Codes on x86 Multicore Processors
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Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
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High-performance hard-input LDPC decoding on multi-core devices for optical space links
inferred← citeshttps://doi.org/10.1109/access.2016.2594265openalex-snapshot
A Survey on Programmable LDPC Decoders
inferred← citeshttps://doi.org/10.1109/access.2025.3527028openalex-snapshot
Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors
inferred← citeshttps://doi.org/10.1109/aero.2019.8742225openalex-snapshot
Scaling the Fast x86 DVB-S2 Decoder to 1 Gbps
inferred← citeshttps://doi.org/10.1109/aero47225.2020.9172605openalex-snapshot
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