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A 90nm low-power FPGA for battery-powered applications
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/cicc.2003.1249359openalex-snapshot
Leakage power analysis of a 90nm FPGA
inferredcites →https://doi.org/10.1109/cicc.2005.1568637openalex-snapshot
Heterogeneous routing architecture for low-power FPGA fabric
inferredcites →https://doi.org/10.1109/cicc.2006.320938openalex-snapshot
Determination of Power Gating Granularity for FPGA Fabric
inferredcites →https://doi.org/10.1109/fpt.2002.1188684openalex-snapshot
Power-aware technology mapping for LUT-based FPGAs
inferredcites →https://doi.org/10.1109/iccad.2003.159755openalex-snapshot
On the interaction between power-aware FPGA CAD Algorithms
inferredcites →https://doi.org/10.1109/iccad.2004.1382647openalex-snapshot
Low-power programmable routing circuitry for FPGAs
inferredcites →https://doi.org/10.1109/iccad.2004.1382678openalex-snapshot
Vdd programmability to reduce FPGA interconnect power
inferredcites →https://doi.org/10.1109/isscc.1996.488556openalex-snapshot
A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application
inferredcites →https://doi.org/10.1109/isscc.1999.759071openalex-snapshot
High speed: not the only way to exploit the intrinsic computational power of silicon
inferredcites →https://doi.org/10.1109/isscc.2005.1493907openalex-snapshot
90nm low leakage SoC design techniques for wireless applications
inferredcites →https://doi.org/10.1109/lpe.2002.146700openalex-snapshot
Standby power management for a 0.18/spl mu/m microprocessor
inferredcites →https://doi.org/10.1117/12.512542openalex-snapshot
An efficient JPEG2000 encoder implemented on a platform FPGA
inferredcites →https://doi.org/10.1145/1120725.1120986openalex-snapshot
Methodology for high level estimation of FPGA power consumption
inferredcites →https://doi.org/10.1145/313817.313920openalex-snapshot
The design of a low energy FPGA
inferredcites →https://doi.org/10.1145/566408.566413openalex-snapshot
Standby power management for a 0.18μm microprocessor
inferredcites →https://doi.org/10.1145/871506.871535openalex-snapshot
Design methodology for fine-grained leakage control in MTCMOS
inferredcites →https://doi.org/10.1145/968280.968285openalex-snapshot
Evaluation of low-leakage design techniques for field programmable gate arrays
inferredcites →https://doi.org/10.1145/968280.968287openalex-snapshot
Active leakage power optimization for FPGAs
inferredcites →https://doi.org/10.1145/968280.968288openalex-snapshot
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
inferredcites →https://doi.org/10.1145/968280.968289openalex-snapshot
Reducing leakage energy in FPGAs using region-constrained placement
inferredcites →https://doi.org/10.1145/996566.996767openalex-snapshot
FPGA power reduction using configurable dual-Vdd
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs
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First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
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Charge recycling for power reduction in FPGA interconnect
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A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm
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Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs
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Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage
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Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components
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Evaluation of granularity on threshold voltage control in flex power FPGA
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An FPGA architecture supporting dynamically controlled power gating
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An FPGA with power-gated switch blocks
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Single chip FPGA based realization of arbitrary waveform generator using rademacher and walsh functions
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Hybrid reconfigurable architecture for low power digital signal processing system
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Low-power Concepts for FPGAs in Applications with limited Energy Resources
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Realization of algorithm for the computation of third-order cross moments using FPGA
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Communication-Aware Module Placement for Power Reduction in Large FPGA Designs
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A New Approach for Arbitrary Waveform Generation using FPGA and Orthogonal Functions
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Exploring the Energy Consumption of Data Sorting Algorithms in Embedded and Mobile Environments
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Power-Aware High-Level Synthesis Flow for Mapping FPGA Designs
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Lightweight Cryptography for FPGAs
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RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT
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Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs
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A Source-Level Energy Optimization Framework for Mobile Applications
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Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
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Performance Benefits of Monolithically Stacked 3-D FPGA
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Input Vector Reordering for Leakage Power Reduction in FPGAs
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Adaptive Energy Management for Dynamically Reconfigurable Processors
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An Ensemble Learning Approach forIn-SituMonitoring of FPGA Dynamic Power
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Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs
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