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Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/2.612253openalex-snapshot

A single-chip multiprocessor

inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot

Networks on chips: a new SoC paradigm

inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot

Simics: A full system simulation platform

inferredcites →https://doi.org/10.1109/5.920580openalex-snapshot

The future of wires

inferredcites →https://doi.org/10.1109/asic.2001.954688openalex-snapshot

A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)

inferredcites →https://doi.org/10.1109/cicc.2003.1249391openalex-snapshot

Three dimensional CMOS devices and integrated circuits

inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot

A delay model and speculative architecture for pipelined routers

inferredcites →https://doi.org/10.1109/iccad.2004.1382522openalex-snapshot

Problems or opportunities? Beyond the 90nm frontier [Keynote]

inferredcites →https://doi.org/10.1109/iccd.2004.1347939openalex-snapshot

3D processing technology and its impact on iA32 microprocessors

inferredcites →https://doi.org/10.1109/iccd.2005.108openalex-snapshot

Three-dimensional cache design exploration using 3DCacti

inferredcites →https://doi.org/10.1109/iccd.2005.65openalex-snapshot

Implementing caches in a 3D technology for high performance processors

inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot

Optimizing Replication, Communication, and Capacity Allocation in CMPs

inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors

inferredcites →https://doi.org/10.1109/isqed.2006.136openalex-snapshot

Thermal trends in emerging technologies

inferredcites →https://doi.org/10.1109/mdt.2005.136openalex-snapshot

Demystifying 3D ICs: The Pros and Cons of Going Vertical

inferredcites →https://doi.org/10.1109/mdt.2005.138openalex-snapshot

First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration

inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot

Managing Wire Delay in Large Chip-Multiprocessor Caches

inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot

Niagara: A 32-Way Multithreaded Sparc Processor

inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot

Energy- and performance-aware mapping for regular NoC architectures

inferredcites →https://doi.org/10.1109/vlsid.2006.10openalex-snapshot

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

inferredcites →https://doi.org/10.1109/vlsit.2004.1345495openalex-snapshot

The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM

inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot

Low-Latency Virtual-Channel Routers for On-Chip Networks

inferredcites →https://doi.org/10.1145/1080695.1069998openalex-snapshot

Victim Replication

inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot

Optimizing Replication, Communication, and Capacity Allocation in CMPs

inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot

A NUCA substrate for flexible CMP cache sharing

inferredcites →https://doi.org/10.1145/1095890.1095915openalex-snapshot

Design and analysis of an NoC architecture from performance, reliability and energy perspective

inferredcites →https://doi.org/10.1145/1120725.1120787openalex-snapshot

Thermal-driven multilevel routing for 3-D ICs

inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot

The case for a single-chip multiprocessor

inferredcites →https://doi.org/10.1145/339647.339691openalex-snapshot

Clock rate versus IPC

inferredcites →https://doi.org/10.1145/378239.379048openalex-snapshot

Route packets, net wires

inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

inferredcites →https://doi.org/10.1145/981066.981091openalex-snapshot

Technology, performance, and computer-aided design of three-dimensional integrated circuits

inferredcites →https://doi.org/10.1147/rd.494.0589openalex-snapshot

Introduction to the Cell multiprocessor

inferredcites →https://doi.org/10.5555/1015090.1015203openalex-snapshot

2.5D system integration: a design driven system implementation schema

inferredcites →https://doi.org/10.5555/774861.774893openalex-snapshot

Orion: a power-performance simulator for interconnection networks

inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot

Distance associativity for high-performance energy-efficient non-uniform cache architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.3925169openalex-extracted

Comments on Ternary Mathematics and 3D Placement of Logical Elements Justification

inferred← citeshttps://doi.org/10.2139/ssrn.4059142openalex-extracted

inferred← citeshttps://doi.org/10.2139/ssrn.4588564openalex-extracted

Ternary Logic and Energy Transfer Presentation on the Example of a Kerr Electro-Optic Effect

inferred← citeshttps://doi.org/10.1002/9781119973584.ch13openalex-snapshot

Cooperative Caching for Chip Multiprocessors

inferred← citeshttps://doi.org/10.1002/9783527623051.ch27openalex-snapshot

Design for 3D Integration at North Carolina State University

inferred← citeshttps://doi.org/10.1002/jnm.70138openalex-snapshot

Thermal Management in 3D Network on Chip Using Modified XYZ Routing Algorithm

inferred← citeshttps://doi.org/10.1007/978-1-4419-0784-4_8openalex-snapshot

Three-Dimensional Network-on-Chip Architecture

inferred← citeshttps://doi.org/10.1007/978-1-4419-0962-6_9openalex-snapshot

Microprocessor Design Using 3D Integration Technology

inferred← citeshttps://doi.org/10.1007/978-1-4419-6193-8_8openalex-snapshot

System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

inferred← citeshttps://doi.org/10.1007/978-1-4419-6778-7_1openalex-snapshot

Memory Architecture and Management in an NoC Platform

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_10openalex-snapshot

3-D NoC on Inductive Wireless Interconnect

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_2openalex-snapshot

The Promises and Limitations of 3-D Integration

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_5openalex-snapshot

Physical Analysis of NoC Topologies for 3-D Integrated Systems

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_6openalex-snapshot

Three-Dimensional Networks-on-Chip: Performance Evaluation

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_7openalex-snapshot

Asynchronous 3D-NoCs Making Use of Serialized Vertical Links

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_8openalex-snapshot

Design of Application-Specific 3D Networks-on-Chip Architectures

inferred← citeshttps://doi.org/10.1007/978-1-4419-7618-5_9openalex-snapshot

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks

inferred← citeshttps://doi.org/10.1007/978-1-4419-9551-3_6openalex-snapshot

An Energy-Efficient 3D Stacked STT-RAM Cache Architecture for CMPs

inferred← citeshttps://doi.org/10.1007/978-1-4614-4274-5_3openalex-snapshot

Communication Architecture

inferred← citeshttps://doi.org/10.1007/978-1-4614-8274-1_7openalex-snapshot

Path-Based Multicast Routing for 2D and 3D Mesh Networks

inferred← citeshttps://doi.org/10.1007/978-1-4614-8274-1_9openalex-snapshot

Reliable and Adaptive Routing Algorithms for 2D and 3D Networks-on-Chip

inferred← citeshttps://doi.org/10.1007/978-1-4939-2163-8_2openalex-snapshot

3D Integration Technology

inferred← citeshttps://doi.org/10.1007/978-3-030-92525-3_5openalex-snapshot

Communication Networks for Neuromorphic Systems

inferred← citeshttps://doi.org/10.1007/978-3-031-01734-6openalex-snapshot

Multi-Core Cache Hierarchies

inferred← citeshttps://doi.org/10.1007/978-3-031-83089-1_5openalex-snapshot

Communication Networks for Neuromorphic Systems

inferred← citeshttps://doi.org/10.1007/978-3-319-00681-9_2openalex-snapshot

Replacing Different Levels of the Memory Hierarchy with NVMs

inferred← citeshttps://doi.org/10.1007/978-3-319-44586-1_10openalex-snapshot

Fundamentals of Heat Dissipation in 3D IC Packaging

inferred← citeshttps://doi.org/10.1007/978-3-540-74309-5_21openalex-snapshot

Power Consumption and Performance Analysis of 3D NoCs

inferred← citeshttps://doi.org/10.1007/978-3-642-11802-9_13openalex-snapshot

Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip

inferred← citeshttps://doi.org/10.1007/978-3-642-12267-5_1openalex-snapshot

Physical Design Issues in 3-D Integrated Technologies

inferred← citeshttps://doi.org/10.1007/978-3-642-24154-3_29openalex-snapshot

Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study

inferred← citeshttps://doi.org/10.1007/978-3-642-28365-9_28openalex-snapshot

Reconfigurable Multicore Architecture for Dynamic Processor Reallocation

inferred← citeshttps://doi.org/10.1007/978-3-642-45073-0_6openalex-snapshot

Configurable Low-Latency Interconnect for Multi-core Clusters

inferred← citeshttps://doi.org/10.1007/978-3-662-45815-0_4openalex-snapshot

Low Latency Multicasting Scheme for Bufferless Hybrid NoC-Bus 3D On-Chip Networks

inferred← citeshttps://doi.org/10.1007/978-3-662-49283-3_2openalex-snapshot

Partitioning Methods for Multicast in Bufferless 3D Network on Chip

inferred← citeshttps://doi.org/10.1007/978-90-481-3031-3_1openalex-snapshot

Introduction

inferred← citeshttps://doi.org/10.1007/978-90-481-3031-3_9openalex-snapshot

A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]

inferred← citeshttps://doi.org/10.1007/978-94-007-1125-9_15openalex-snapshot

3D Architectures

inferred← citeshttps://doi.org/10.1007/978-94-007-6818-5_26openalex-snapshot

Fault-Tolerant Optimization for Application-Specific Network-on-Chip Architecture

inferred← citeshttps://doi.org/10.1007/978-981-10-6092-2_5openalex-snapshot

Advanced Multicore SoC Interconnects

inferred← citeshttps://doi.org/10.1007/978-981-15-7090-2_13openalex-snapshot

Fundamentals of Heat Dissipation in 3D IC Packaging and Thermal-Aware Design

inferred← citeshttps://doi.org/10.1007/978-981-32-9767-8_27openalex-snapshot

2L-2D Routing for Buffered Mesh Network-on-Chip

inferred← citeshttps://doi.org/10.1007/s00607-013-0378-1openalex-snapshot

Energy reduction in 3D NoCs through communication optimization

inferred← citeshttps://doi.org/10.1007/s10836-013-5373-0openalex-snapshot

Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design

inferred← citeshttps://doi.org/10.1007/s10836-013-5389-5openalex-snapshot

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

inferred← citeshttps://doi.org/10.1007/s11227-011-0577-5openalex-snapshot

Reliability-aware platform optimization for 3D chip multi-processors

inferred← citeshttps://doi.org/10.1007/s11227-012-0865-8openalex-snapshot

Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors

inferred← citeshttps://doi.org/10.1007/s11390-018-1868-6openalex-snapshot

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint

inferred← citeshttps://doi.org/10.1016/b978-0-12-374343-5.00019-8openalex-snapshot

References

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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh

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Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach

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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips

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System-level process variability analysis and mitigation for 3D MPSoCs

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System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

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Efficient OpenMP data mapping for multicore platforms with vertically stacked memory

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Floorplanning exploration and performance evaluation of a new Network-on-Chip

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Partitioning methods for unicast/multicast traffic in 3D NoC architecture

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LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture

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Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing Algorithm

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TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

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A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

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Yield improvement and test cost reduction for TSV based 3D stacked ICs

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Cost Evaluation of Three-Dimensional Network-on-Chip

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CMP network-on-chip overlaid with multi-band RF-interconnect

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Performance and power optimization through data compression in Network-on-Chip architectures

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A low-radix and low-diameter 3D interconnection network design

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A novel architecture of the 3D stacked MRAM L2 cache for CMPs

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Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

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An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth

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Dynamically heterogeneous cores through 3D resource pooling

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Efficient Mapping of Multi-threaded Applications onto 3D Stacked Chip-Multiprocessor

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Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores

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Low power heterogeneous 3D Networks-on-Chip architectures

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On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA

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Optimal data layout for block-level random accesses to scratchpad

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Extended abstract: Trustworthy system security through 3-D integrated hardware

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The Shuffle-Exchange Mesh Topology for 3D NoCs

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Three-Dimensional Layout of On-Chip Tree-Based Networks

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3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling

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Near-optimal oblivious routing on three-dimensional mesh networks

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Ring data location prediction scheme for Non-Uniform Cache Architectures

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Scalable memory fabric for silicon interposer-based multi-core systems

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A DFTR router architecture for 3D Network on Chip

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A Fault Tolerant Bufferless Optical Interconnection Network

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Thermal-Aware Energy Optimization by Synthesizing Firm 3-D Network-on-Chip with Voltage-Frequency Islands

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Low-overhead Routing Algorithm for 3D Network-on-Chip

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Tightly-Coupled Multi-Layer Topologies for 3-D NoCs

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Microprocessor Architecture and Design in Post Exascale Computing Era

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State of art of Network on Chip

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3D Network-on-Chip system communication using minimum number of TSVs

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Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics

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T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs

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MIRA: A Multi-layered On-Chip Interconnect Router Architecture

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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies

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Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips

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Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication

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Effective thermal control techniques for liquid-cooled 3D multi-core processors

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Fast stress analysis for runtime reliability enhancement of 3D IC using artificial neural network

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Design for 3D Integration and Applications

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Performance Evaluation for Three-Dimensional Networks-On-Chip

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Testing Circuit-Partitioned 3D IC Designs

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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology

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Power-Efficient Inter-Layer Communication Architectures for 3D NoC

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A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies

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Adaptive Stackable 3D Cache Architecture for Manycores

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A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing

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A novel 3D crossbar-based chip multiprocessor architecture

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Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

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3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

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Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks

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A Layer-Multiplexed 3D On-Chip Network Architecture

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Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis

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Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

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Leveraging 3D Technology for Improved Reliability

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Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

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Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration

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NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

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LerGAN: A Zero-Free, Low Data Movement and PIM-Based GAN Architecture

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Processor Design in 3D Die-Stacking Technologies

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Network-on-Chip Design Guidelines for Monolithic 3-D Integration

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NEMS based thermal management for 3D many-core system

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Highly-scalable 3D CLOS NOC for many-core CMPs

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Approaching Ideal NoC Latency with Pre-Configured Routes

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Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

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Scalability of network-on-chip communication architecture for 3-D meshes

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Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures

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Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture

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Using packet information for efficient communication in NoCs

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An analysis of designing 2D/3D chip multiprocessor wit different cache architecture

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Research and practices on 3D networks-on-chip architectures

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An adaptive router architecture for heterogeneous 3D Networks-on-Chip

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Optimising Heterogeneous 3D Networks-on-Chip

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3D-PIM NoCs with Multiple Subnetworks: A Performance and Power Evaluation

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Online Scheduling of Applications on 3D Stacked Large Chip Multiprocessor

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A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication

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