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Multiplierless multiple constant multiplication

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1002/spe.4380160704openalex-snapshot

Multiplication by integer constants

inferredcites →https://doi.org/10.1049/ip-cds:19941191openalex-snapshot

Constant integer multiplication using minimum adders

inferredcites →https://doi.org/10.1049/ip-g-2.1991.0066openalex-snapshot

Primitive operator digital filters

inferredcites →https://doi.org/10.1109/12.795126openalex-snapshot

Closed-form expression for the average weight of signed-digit representations

inferredcites →https://doi.org/10.1109/43.739059openalex-snapshot

A new algorithm for elimination of common subexpressions

inferredcites →https://doi.org/10.1109/78.969511openalex-snapshot

Fast multiplierless approximations of the DCT with the lifting scheme

inferredcites →https://doi.org/10.1109/82.466647openalex-snapshot

Use of minimum-adder multiplier blocks in FIR digital filters

inferredcites →https://doi.org/10.1109/82.539000openalex-snapshot

Subexpression sharing in filters using canonic signed digit multipliers

inferredcites →https://doi.org/10.1109/82.959867openalex-snapshot

FIR filter synthesis algorithms for minimizing the delay and the number of adders

inferredcites →https://doi.org/10.1109/iccad.2004.1382567openalex-snapshot

Custom-optimized multiplierless implementations of DSP algorithms

inferredcites →https://doi.org/10.1109/icecs.2001.957791openalex-snapshot

Cascaded coefficient number systems lead to FIR filters of striking computational efficiency

inferredcites →https://doi.org/10.1109/iscas.2002.1009780openalex-snapshot

Extended results for minimum-adder constant integer multipliers

inferredcites →https://doi.org/10.1109/iscas.2002.1010818openalex-snapshot

Designing multiplier blocks with low logic depth

inferredcites →https://doi.org/10.1109/iscas.2003.1206140openalex-snapshot

Proceedings Of The 2003 IEEE International Symposium On Circuits And systems

inferredcites →https://doi.org/10.1109/iscas.2004.1328709openalex-snapshot

Using all signed-digit representations to design single integer multipliers using subexpression elimination

inferredcites →https://doi.org/10.1109/lsp.2002.804419openalex-snapshot

Multiplierless approximation of transforms with adder constraint

inferredcites →https://doi.org/10.1109/tassp.1984.1164433openalex-snapshot

Some complexity issues in digital signal processing

inferredcites →https://doi.org/10.1109/tec.1961.5219227openalex-snapshot

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

inferredcites →https://doi.org/10.1109/tsp.2004.827177openalex-snapshot

Complexity Reduction of Digital Filters Using Shift Inclusive Differential Coefficients

inferredcites →https://doi.org/10.1145/322217.322228openalex-snapshot

Variations on the Common Subexpression Problem

inferredcites →https://doi.org/10.1145/996566.996787openalex-snapshot

Multiple constant multiplication by time-multiplexed mapping of addition chains

inferredcites →https://doi.org/10.2307/2317055openalex-snapshot

The Art of Computer Programming. Volume 2: Seminumerical Algorithms.

inferredcites →https://doi.org/10.5555/602902.602915openalex-snapshot

FIR filter synthesis algorithms for minimizing the delay and the number of adders

What points at this work

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Efficient structural adder pipelining in transposed form FIR filters

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A new hybrid CSE technique for multiplier-less FIR filter

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Investigation on power consumption of product accumulation block for multiplierless FIR filters

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Design of Multiplierless M-channel Cosine Modulated Filterbank using Hybrid CSE Technique

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State Transition Graph-Based Pipelined Sequential Multiplier

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Efficient VLSI architecture for FIR filter using DA-RNS

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A CMOS-MEMS Thermoelectric Infrared Sensor

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Bit-Level Optimization of Shift-and-Add Based FIR Filters

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Design flow for the generation of optimized FIR filters

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Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach

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Hybrid multiple constant multiplication for FPGAs

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Constant Matrix Multiplication with Ternary Adders

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Review of Multiplierless Fir Filter Design Based On Graph Based Optimization

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Process Variation and Voltage Scaling Optimization Techniques for Processing Signals Using Multirate

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An Optimization in Conventional Shift &Add Multiplier for Area-Efficient Implementation on FPGA

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Novel Approach of Digit Serial Multiple Constant Multiplication in DSP Applications

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Computation of Design Metrics in Online Arithmetic Networks

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Optimization technique of FIR filter using digit serial architecture

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Design of digit serial FIR Filter for power optimization

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Generalized overlapping digit patterns for multi-dimensional sub-expression sharing

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Reconfigurable architecture for FIR filter with low power consumption

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A low energy HEVC sub-pixel interpolation hardware

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High-throughput and low-cost hardware-oriented integer transforms for HEVC

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High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation

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A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards

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Performance evaluation of FIR filters using digit serial architectures

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VHDL generation of optimized FIR filters

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Multi-Constant Multiplication Optimization Based on Common Sub-Expression Elimination

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A new binary arithmetic for finite-word-length linear controllers: MEMS applications

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Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH

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Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them

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FPGA-Based Resource-Shared Implementation of 1D DCT Using a Single Multiplier and Adder

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A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems

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Switching activity estimation for shift-and-add based constant multipliers

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Subexpression encoded extrapolated impulse response FIR filter with perfect residual compensation

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On the complexity reduction of polyphase linear phase FIR filters with symmetric coefficient implementation

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Low-complexity reconfigurable complex constant multiplication for FFTs

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Estimation of the switching activity in shift-and-add based computations

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Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication

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Truncated MCM using pattern modification for FIR filter implementation

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Low-complexity linear phase fir filters in cascade form

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Bit-parallel Multiple Constant Multiplication using Look-Up Tables on FPGA

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Minimum adder depth multiple constant multiplication algorithm for low power FIR filters

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Optimization of area in digit-serial Multiple Constant Multiplications at gate-level

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Pipelined adder graph optimization for high speed multiple constant multiplication

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Multiple real-constant multiplication with improved cost model and greedy and optimal searches

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Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs

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High-speed multiplier block design based on bit-level critical path optimization

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ECHO: A novel method for the multiplierless design of constant array vector multiplication

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Integer-coefficient FIR filter sharpening for equiripple stopbands and maximally flat passbands

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Area-time efficient realization of multiple constant multiplication

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Fine-grained pipelining for multiple constant multiplications

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A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding

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Efficient Time-Multiplexed Realization of Feedforward Artificial Neural Networks

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Multiversion Low-Power Hardware Accelerator for the AV1 Interpolation Filters

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Truncated Multiple Constant Multiplication with Minimal Number of Full Adders

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Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders

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Enhancing Common Subexpression Elimination Algorithms

showing the first 200 of 406

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