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New cache designs for thwarting software cache-based side channel attacks

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/3-540-48285-7_33openalex-snapshot
Linear Cryptanalysis Method for DES Cipher
inferredcites →https://doi.org/10.1007/3-540-48405-1_25openalex-snapshot
Differential Power Analysis
inferredcites →https://doi.org/10.1007/bf00630563openalex-snapshot
Differential cryptanalysis of DES-like cryptosystems
inferredcites →https://doi.org/10.1016/s0377-0427(91)90073-sopenalex-snapshot
Department of Computer Science
inferredcites →https://doi.org/10.1145/1024393.1024403openalex-snapshot
HIDE
inferredcites →https://doi.org/10.1145/996566.996771openalex-snapshot
Security as a new dimension in embedded system design

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Hardware-Enhanced Security for Cloud Computing
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Optimal Partitioning of LLC in CAT-enabled CPUs to Prevent Side-Channel Attacks
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Leaky Controller: Cross-VM Memory Controller Covert Channel on Multi-core Systems
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Cloud Computing Security: Hardware-Based Attacks and Countermeasures
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A Study on Microarchitectural Covert Channel Vulnerabilities in Infrastructure-as-a-Service
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Security of Emerging Memory Chips
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On the Cost-Effectiveness of TrustZone Defense on ARM Platform
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Integrating Information Flow Tracking into High-Level Synthesis Design Flow
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An Investigation of Microarchitectural Cache-Based Side-Channel Attacks from a Digital Forensic Perspective: Methods of Exploits and Countermeasures
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HyperDetector: Detecting, Isolating, and Mitigating Timing Attacks in Virtualized Environments
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Formal Hardware/Software Models for Cache Locking Enabling Fast and Secure Code
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Fast and Efficient Secure L1 Caches for SMT
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Countermeasures for Timing Attacks
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C5: Cross-Cores Cache Covert Channel
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Flush+Flush: A Fast and Stealthy Cache Attack
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Cross-VM Attacks: Attack Taxonomy, Defense Mechanisms, and New Directions
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Putting Trojans on the Horns of a Dilemma: Redundancy for Information Theft Detection
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Incentive Compatible Moving Target Defense against VM-Colocation Attacks in Clouds
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Automatic Quantification of Cache Side-Channels
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Building Technologies that Help Cyber-Defense: Hardware-enabled Trust
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Cache Based Side-Channel Attacks
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Secure Processor Architectures
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A Formal Analysis of Prefetching in Profiled Cache-Timing Attacks on Block Ciphers
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Covert Timing Channels Exploiting Cache Coherence Hardware: Characterization and Defense
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System-Level Non-interference of Constant-Time Cryptography. Part I: Model
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System-Level Non-interference of Constant-Time Cryptography. Part II: Verified Static Analysis and Stealth Memory
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An optimistic technique to detect Cache based Side Channel attacks in Cloud
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Adaptive caches as a defense mechanism against cache side-channel attacks
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A Survey of Side-Channel Attacks on Caches and Countermeasures
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Survey of Microarchitectural Side and Covert Channels, Attacks, and Defenses
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Analysis of Secure Caches Using a Three-Step Model for Timing-Based Attacks
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A Survey on Cache Timing Channel Attacks for Multicore Processors
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A survey of security issues for cloud computing
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Secure hybrid replacement policy: Mitigating conflict-based cache side channel attacks
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Verifying cache architecture vulnerabilities using a formal security verification flow
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TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks
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Improving security in cache memory by power efficient scrambling technique
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MemWander: Memory Dynamic Remapping via Hypervisor Against Cache-Based Side-Channel Attacks
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Meet the Sherlock Holmes’ of Side Channel Leakage: A Survey of Cache SCA Detection Techniques
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WHISPER: A Tool for Run-Time Detection of Side-Channel Attacks
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Defending Against Co-Residence Attack in Energy-Efficient Cloud: An Optimization Based Real-Time Secure VM Allocation Strategy
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Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
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Evaluation of Machine Learning-based Detection against Side-Channel Attacks on Autonomous Vehicle
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Data scrambling in memories: A security measure
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Analyzing The Security of The Cache Side Channel Defences With Attack Graphs
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A Security Verification Template to Assess Cache Architecture Vulnerabilities
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SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks
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Interleaved scrambling technique: A novel low-power security layer for cache memories
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Hardware/Software Obfuscation against Timing Side-channel Attack on a GPU
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SCALE: Secure and Scalable Cache Partitioning
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Hardware-software integrated approaches to defend against software cache-based side channel attacks
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A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks
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Are Coherence Protocol States Vulnerable to Information Leakage?
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Leaking Information Through Cache LRU States
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Abusing Cache Line Dirty States to Leak Information in Commercial Processors
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DAPPER: A Performance-Attack-Resilient Tracker for RowHammer Defense
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TrustGeM: Dynamic trusted environment generation for chip-multiprocessors
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COTSknight: Practical Defense against Cache Timing Channel Attacks using Cache Monitoring and Partitioning Technologies
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Scheduling, Isolation, and Cache Allocation: A Side-Channel Defense
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A novel cache bank timing attack
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An optimized VM Allocation Strategy to Make a Secure and Energy-Efficient Cloud Against Co-residence Attack
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Protecting cache memories through data scrambling technique
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HybriDG: Hybrid Dynamic Time Warping and Gaussian Distribution Model for Detecting Emerging Zero-Day Microarchitectural Side-Channel Attacks
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Capacity of EM Side Channel Created by Instruction Executions in a Processor
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CASM: A Generalizable and Accessible Security Metric to Evaluate Security of Cache Architectures
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SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features
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Side-channel vulnerability factor: A metric for measuring information leakage
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TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software
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Exploiting Configurability as a Defense against Cache Side Channel Attacks
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Designing Secure TLBs
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CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches
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CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping
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CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
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Mitigating shift-based covert-channel attacks in racetrack last level caches
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Cache Based Side-Channel Attacks: A Survey
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Seeds of SEED: A Side-Channel Resilient Cache Skewed by a Linear Function over a Galois Field
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PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring
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Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing
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Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors
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Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It
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Scatter and Split Securely: Defeating Cache Contention and Occupancy Attacks
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Ceviche: Capability-Enhanced Secure Virtualization of Caches
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Leaking Information Through Cache LRU States in Commercial Processors and Secure Caches
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Preventing Coherence State Side Channel Leaks Using TimeCache
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Information Leakage Attacks Exploiting Cache Replacement in Commercial Processors
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An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
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Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks
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Reducing Timing Side-Channel Information Leakage Using 3D Integration
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Adaptive Compiler Strategies for Mitigating Timing Side Channel Attacks
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TITAN: Uncovering the Paradigm Shift in Security Vulnerability at Near-Threshold Computing
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Electromagnetic Side Channel Information Leakage Created by Execution of Series of Instructions in a Computer Processor
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Deep Learning-Based Detection for Multiple Cache Side-Channel Attacks
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Security-Aware Task Mapping Reducing Thermal Side Channel Leakage in CMPs
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Secure Queryable Dynamic Graphs using Blockchain
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EDL: Efficient Data-Oblivious Loops
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FairSDP: Fair and Secure Dynamic Cache Partitioning
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Detailed tracking of program control flow using analog side-channel signals: a promise for IoT malware detection and a threat for many cryptographic implementations
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Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
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Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
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SPMVisor
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Compiler mitigations for time attacks on modern x86 processors
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Architectural support for secure virtualization under a vulnerable hypervisor
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Side-channel vulnerability factor
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TimeWarp
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Virtualization
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Co-Location-Resistant Clouds
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Disruptive prefetching
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A Study on Power Side Channels on Mobile Devices
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Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures
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How secure is your cache against side-channel attacks?
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BranchScope
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Cache timing side-channel vulnerability checking with computation tree logic
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BranchScope
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CacheGuard
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In Hardware We Trust
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EA-PLRU
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MasQ
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Towards Provable Timing-Channel Prevention
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Beyond Cache Attacks
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Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses
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Constantine: Automatic Side-Channel Resistance Using Efficient Control and Data Flow Linearization
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Interpretable noninterference measurement and its application to processor designs
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Write Me and I’ll Tell You Secrets – Write-After-Write Effects On Intel CPUs
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CacheFX: A Framework for Evaluating Cache Security
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RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks
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Survey of CPU Cache-Based Side-Channel Attacks: Systematic Analysis, Security Models, and Countermeasures
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Advancing Edge Artificial Intelligence
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Efficient AI-based Attack Detection Methods for Sensitive Edge Devices and Systems
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A Study of Mitigation Methods for Speculative Cache Side Channel Attacks
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Advancing Edge Artificial Intelligence
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PhantomCache: Obfuscating Cache Conflicts with Localized Randomization
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Chunked-Cache: On-Demand and Scalable Cache Isolation for Security Architectures
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BliMe: Verifiably Secure Outsourced Computation with Hardware-Enforced Taint Tracking
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SENSE: Enhancing Microarchitectural Awareness for TEEs via Subscription-Based Notification
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TEE-SHirT: Scalable Leakage-Free Cache Hierarchies for TEEs
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Hardware-based cyber threats: attack vectors and defence techniques
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Know Thy Neighbor: Crypto Library Detection in Cloud
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Driftor: mitigating cloud-based side-channel attacks by switching and migrating multi-executor virtual machines
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Eş zamanlı çok işlem parçacıklı işlemcilerde adalet için güvenli önbellek paylaşımı
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Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits
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Statistics in side channel analysis
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Algorithms for network resource allocation under adversarial dynamics and assignment constraints
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An Anti-Side-Channel Virtual CPU Scheduling Algorithm Based on Leakage Evaluation for Virtual Machine Security
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A new secure proxy-based distributed virtual machines management in mobile cloud computing
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Tools for the Evaluation and Choice of Countermeasures against Side-Channel Attacks
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Analysis and design of microarchitectural side-channel attacks and countermeasures
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Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis
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Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks
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Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
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Cloud Workload Allocation Approaches for Quality of Service Guarantee and Cybersecurity Risk Management
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Locality Based Cache Side-channel Attack Detection
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Side Channel Attacks
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Defensive Countermeasures Towards Addressing Cloud Security Attacks
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Defensive Countermeasures Towards Addressing Cloud Security Attacks
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CacheSCDefender: VMM-based Comprehensive Framework against Cache-based Side-channel Attacks
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Proxy-3S
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Adaptive Noise Injection against Side-Channel Attacks on ARM Platform
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Bluethunder: A 2-level Directional Predictor Based Side-Channel Attack against SGX
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Security Model for Randomization-based Protected Caches
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Risky Translations: Securing TLBs against Timing Side Channels
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Ensuing Security in a Proposed Tertiary Institution Cloud Computing Environment: Introducing a NoHype Framework to the Private Cloud as a Way of Securing the IaaS Model
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Hardware Attack Mitigation Techniques Analysis
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Cloud Computing: Security and Reliability Issues
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Self-healing and secure low-power memory systems
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Non-functional considerations of time-randomized processor architectures
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Security aspects related cache memories in the system files
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Unified isolation architecture and mechanisms against side channel attacks for decentralized cloud infrastructures
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Timing attacks : modelization and protections
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