On the public citation graph
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
0 signed · 97 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-012-0828-0openalex-snapshot
Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration
inferred← citeshttps://doi.org/10.1016/j.applthermaleng.2019.114832openalex-snapshot
A novel thermal management scheme for 3D-IC chips with multi-cores and high power density
inferred← citeshttps://doi.org/10.1016/j.applthermaleng.2025.125920openalex-snapshot
Assessment of rib filling mode and arrangement impact on thermal management in chiplet microsystems with multiple hot spots and high power density
inferred← citeshttps://doi.org/10.1016/j.bdr.2017.06.004openalex-snapshot
Partial Rollback-based Scheduling on In-memory Transactional Data Grids
inferred← citeshttps://doi.org/10.1016/j.cola.2019.02.001openalex-snapshot
Supporting multi-view development for mobile applications
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2015.06.004openalex-snapshot
Cloud-based power estimation and power-aware scheduling for embedded systems
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2023.108827openalex-snapshot
Efficient parallel implementation of Gaussian Mixture Model background subtraction algorithm on an embedded multi-core Digital Signal Processor
inferred← citeshttps://doi.org/10.1016/j.cose.2020.102072openalex-snapshot
Semantics-aware obfuscation scheme prediction for binary
inferred← citeshttps://doi.org/10.1016/j.enconman.2019.04.028openalex-snapshot
Performance optimization of cascaded and non-cascaded thermoelectric devices for cooling computer chips
inferred← citeshttps://doi.org/10.1016/j.future.2015.09.018openalex-snapshot
Dynamic core allocation for energy efficient video decoding in homogeneous and heterogeneous multicore architectures
inferred← citeshttps://doi.org/10.1016/j.future.2017.01.009openalex-snapshot
The home-forwarding mechanism to reduce the cache coherence overhead in next-generation CMPs
inferred← citeshttps://doi.org/10.1016/j.future.2018.02.038openalex-snapshot
DWARM: A wear-aware memory management scheme for in-memory file systems
inferred← citeshttps://doi.org/10.1016/j.future.2019.07.035openalex-snapshot
Towards the design of efficient hash-based indexing scheme for growing databases on non-volatile memory
inferred← citeshttps://doi.org/10.1016/j.future.2020.01.051openalex-snapshot
Accelerated CPU–GPUs implementations for quaternion polar harmonic transform of color images
inferred← citeshttps://doi.org/10.1016/j.jlamp.2018.06.002openalex-snapshot
Best-by-simulations: A framework for comparing efficiency of reconfigurable architectures on workloads with deadlines
inferred← citeshttps://doi.org/10.1016/j.jocs.2024.102516openalex-snapshot
A multiple sclerosis two-compartmental differential equation computational model 3D simulation using OpenCL
inferred← citeshttps://doi.org/10.1016/j.jpdc.2011.03.005openalex-snapshot
Resolving a L2-prefetch-caused parallel nonscaling on Intel Core microarchitecture
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.05.006openalex-snapshot
A collaborative CPU–GPU approach for principal component analysis on mobile heterogeneous platforms
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.jpdc.2022.03.016openalex-snapshot
An SMDP-based approach to thermal-aware task scheduling in NoC-based MPSoC platforms
inferred← citeshttps://doi.org/10.1016/j.jpdc.2025.105135openalex-snapshot
Towards efficient program execution on edge-cloud computing platforms
inferred← citeshttps://doi.org/10.1016/j.jss.2015.11.042openalex-snapshot
Mobile device power models for energy efficient dynamic offloading at runtime
inferred← citeshttps://doi.org/10.1016/j.jss.2016.07.032openalex-snapshot
ReSeer: Efficient search-based replay for multiprocessor virtual machines
inferred← citeshttps://doi.org/10.1016/j.jss.2022.111247openalex-snapshot
WDBT: Non-volatile memory wear characterization and mitigation for DBT systems
inferred← citeshttps://doi.org/10.1016/j.memori.2022.100014openalex-snapshot
Gray counters for non-volatile memories
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.07.007openalex-snapshot
LDBR: Low-deflection bufferless router for cost-sensitive network-on-chip design
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.04.005openalex-snapshot
Design and implementation of instruction indirection for embedded software obfuscation
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.11.015openalex-snapshot
Odd/Even Invert coding for phase change memory with thermal crosstalk
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.03.005openalex-snapshot
SDNoC: Software defined network on a chip
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.05.018openalex-snapshot
The AXIOM platform for next-generation cyber physical systems
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.06.012openalex-snapshot
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.08.007openalex-snapshot
ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.09.004openalex-snapshot
TELEPORT: Hardware/software alternative to CUDA shared memory programming
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.12.001openalex-snapshot
SIMD stealing: Architectural support for efficient data parallel execution on multicores
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103082openalex-snapshot
A study on the performance impact of programmable logic controllers based on enhanced architecture and organization
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104462openalex-snapshot
An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104464openalex-snapshot
A router architecture with dual input and dual output channels for Networks-on-Chip
inferred← citeshttps://doi.org/10.1016/j.micpro.2022.104711openalex-snapshot
Variation aware power management for GPU memories
inferred← citeshttps://doi.org/10.1016/j.micpro.2023.104971openalex-snapshot
GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory
inferred← citeshttps://doi.org/10.1016/j.micpro.2023.104975openalex-snapshot
On the interactions between ILP and TLP with hardware transactional memory
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114154openalex-snapshot
DLBF: A low overhead wear leveling algorithm for embedded systems with hybrid memory
inferred← citeshttps://doi.org/10.1016/j.microrel.2023.114939openalex-snapshot
Enhancing the lifetime of STT-RAM using compression based wear leveling technique
inferred← citeshttps://doi.org/10.1016/j.osn.2019.03.004openalex-snapshot
SMONoC: Optical network-on-chip using a statistical multiplexing strategy
inferred← citeshttps://doi.org/10.1016/j.parco.2016.01.010openalex-snapshot
A dynamic block-level execution profiler
inferred← citeshttps://doi.org/10.1016/j.pmcj.2015.10.011openalex-snapshot
Constella: Crowdsourced system setting recommendations for mobile devices
inferred← citeshttps://doi.org/10.1016/j.softx.2023.101329openalex-snapshot
TDF: A compact file format plugin for FEniCS
inferred← citeshttps://doi.org/10.1016/j.suscom.2017.05.005openalex-snapshot
Thermal-aware management techniques for cyber-physical systems
inferred← citeshttps://doi.org/10.1016/j.suscom.2025.101156openalex-snapshot
PPAS-MiCs: Peak-power-aware scheduling of fault-tolerant mixed-criticality systems
inferred← citeshttps://doi.org/10.1016/j.swevo.2019.100574openalex-snapshot
Frequent pattern mining assisted energy consumption evolutionary optimization approach based on surrogate model at GCC compile time
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.06.001openalex-snapshot
Energy efficient task allocation for hybrid main memory architecture
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.10.001openalex-snapshot
Provisioning of power event APIs as a mobile OS facility
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.11.002openalex-snapshot
An energy-efficient encryption mechanism for NVM-based main memory in mobile systems
inferred← citeshttps://doi.org/10.1016/j.sysarc.2016.12.001openalex-snapshot
TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips
inferred← citeshttps://doi.org/10.1016/j.sysarc.2017.10.001openalex-snapshot
Accurate power modeling of modern mobile application processors
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.101658openalex-snapshot
Quail: Using NVM write monitor to enable transparent wear-leveling
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102364openalex-snapshot
Process variation aware DRAM-Cache resizing
inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102734openalex-snapshot
Enabling PIM-based AES encryption for online video streaming
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.103008openalex-snapshot
A survey on techniques for improving Phase Change Memory (PCM) lifetime
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103174openalex-snapshot
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103481openalex-snapshot
BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures
inferred← citeshttps://doi.org/10.1016/j.vlsi.2022.03.004openalex-snapshot
Improving the thermal reliability of photonic chiplets on multicore processors
inferred← citeshttps://doi.org/10.1039/d1ra02210eopenalex-snapshot
Enhanced reliability of phase-change memory via modulation of local structure and chemical bonding by incorporating carbon in Ge 2 Sb 2 Te 5
inferred← citeshttps://doi.org/10.1109/ccgrid64434.2025.00023openalex-snapshot
SoftGuide: A Hardware-Software Co-design Predictor for Data-Dependent Branches
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00033openalex-snapshot
BeaconGNN: Large-Scale GNN Acceleration with Out-of-Order Streaming In-Storage Computing
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00081openalex-snapshot
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/iseda65950.2025.11101285openalex-snapshot
ArchBot: A Labour-free Processor Architecture Design Framework via Experienced LLM
inferred← citeshttps://doi.org/10.1109/ises58672.2023.00013openalex-snapshot
A Neural Network-Based Approach to Dynamic Core Morphing for AMPs
inferred← citeshttps://doi.org/10.1109/mcsoc57363.2022.10023992openalex-snapshot
Traffic-Aware Energy-Efficient Hybrid Input Buffer Design for On-Chip Routers
inferred← citeshttps://doi.org/10.1109/upcon56432.2022.9986479openalex-snapshot
Analyzing Binary Tree based Topology Configuration for Energy Efficient Multicore Architectures
inferred← citeshttps://doi.org/10.1109/vts65138.2025.11022867openalex-snapshot
Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies
inferred← citeshttps://doi.org/10.1145/3418498openalex-snapshot
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning
inferred← citeshttps://doi.org/10.1145/3470496.3527412openalex-snapshot
Axiomatic hardware-software contracts for security
inferred← citeshttps://doi.org/10.1145/3490148.3538578openalex-snapshot
Performance Analysis and Modelling of Concurrent Multi-access Data Structures
inferred← citeshttps://doi.org/10.1145/3490422.3502357openalex-snapshot
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication
inferred← citeshttps://doi.org/10.1145/3575693.3575696openalex-snapshot
SpecPMT: Speculative Logging for Resolving Crash Consistency Overhead of Persistent Memory
inferred← citeshttps://doi.org/10.1145/3575693.3575700openalex-snapshot
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
inferred← citeshttps://doi.org/10.1145/3583781.3590233openalex-snapshot
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning
inferred← citeshttps://doi.org/10.1145/3613424.3614285openalex-snapshot
Simultaneous and Heterogenous Multithreading
inferred← citeshttps://doi.org/10.1145/3634737.3637651openalex-snapshot
Beyond Over-Protection: A Targeted Approach to Spectre Mitigation and Performance Optimization
inferred← citeshttps://doi.org/10.1145/3649329.3655924openalex-snapshot
Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows
inferred← citeshttps://doi.org/10.1145/3658617.3697543openalex-snapshot
TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning
inferred← citeshttps://doi.org/10.1145/3676536.3676696openalex-snapshot
CAMSHAP: Accelerating Machine Learning Model Explainability with Analog CAM
inferred← citeshttps://doi.org/10.1145/3689334openalex-snapshot
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories
inferred← citeshttps://doi.org/10.1145/3727638openalex-snapshot
Supporting Dynamic Program Sizes in Deep Learning-Based Cost Models for Code Optimization
inferred← citeshttps://doi.org/10.4995/thesis/10251/165254openalex-snapshot
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-166153openalex-snapshot
Exploiting task-based programming models for resilience
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.