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CACTI-FinFET

https://doi.org/10.1145/2024724.2024918

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1016/j.sse.2003.12.030openalex-snapshot

A process/physics-based compact model for nonclassical CMOS device and circuit design

inferredcites →https://doi.org/10.1109/date.2010.5457167openalex-snapshot

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability

inferredcites →https://doi.org/10.1109/iccd.2007.4601953openalex-snapshot

CMOS logic design with independent-gate FinFETs

inferredcites →https://doi.org/10.1109/isqed.2007.79openalex-snapshot

From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis

inferredcites →https://doi.org/10.1109/isqed.2010.5450554openalex-snapshot

Die-level leakage power analysis of FinFET circuits considering process variations

inferredcites →https://doi.org/10.1109/socc.2008.4641521openalex-snapshot

Low power 8T SRAM using 32nm independent gate FinFET technology

inferredcites →https://doi.org/10.1109/soi.2006.284456openalex-snapshot

FinFET SRAM with Enhanced Read / Write Margins

inferredcites →https://doi.org/10.1109/tcad.2005.850834openalex-snapshot

Statistical timing analysis under spatial correlations

inferredcites →https://doi.org/10.1109/tcad.2009.2017431openalex-snapshot

A Novel Table-Based Approach for Design of FinFET Circuits

inferredcites →https://doi.org/10.1109/ted.2007.894605openalex-snapshot

Temperature Dependence of Substrate and Drain Currents in Bulk FinFETs

inferredcites →https://doi.org/10.1109/vlsid.2007.182openalex-snapshot

A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

inferredcites →https://doi.org/10.1145/1077603.1077607openalex-snapshot

FinFET-based SRAM design

inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot

McPAT

inferredcites →https://doi.org/10.1145/1687399.1687495openalex-snapshot

Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization

inferredcites →https://doi.org/10.1145/775832.775920openalex-snapshot

Parameter variations and impact on circuits and microarchitecture

inferredcites →https://doi.org/10.5555/1326073.1326230openalex-snapshot

The effect of process variation on device temperature in FinFET circuits

inferredcites →https://doi.org/10.5555/996070.1009993openalex-snapshot

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.mejo.2021.105116openalex-snapshot

FinFET based SRAMs in Sub-10nm domain

inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.12.003openalex-snapshot

Full-VDD and near-threshold performance of 8T FinFET SRAM cells

inferred← citeshttps://doi.org/10.1017/cbo9781316156148.003openalex-snapshot

FinFETs: from devices to architectures

inferred← citeshttps://doi.org/10.1049/pbcs030e_ch3openalex-snapshot

Nanoscale FinFET devices for PVT-aware SRAM

inferred← citeshttps://doi.org/10.1109/candarw51189.2020.00085openalex-snapshot

A Conflict-Aware Capacity Control Mechanism for Last-Level Cache

inferred← citeshttps://doi.org/10.1109/iccad.2015.7372611openalex-snapshot

TEI-Turbo: temperature effect inversion-aware turbo boost for finfet-based multi-core systems

inferred← citeshttps://doi.org/10.1109/isvlsi.2014.94openalex-snapshot

FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices

inferred← citeshttps://doi.org/10.1109/nanoarch.2015.7180587openalex-snapshot

Computation-in-memory based parallel adder

inferred← citeshttps://doi.org/10.1109/tcad.2017.2666721openalex-snapshot

Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems

inferred← citeshttps://doi.org/10.1109/tvlsi.2013.2260569openalex-snapshot

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2360067openalex-snapshot

FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3123112openalex-snapshot

FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies

inferred← citeshttps://doi.org/10.1145/2491678openalex-snapshot

Design space exploration of FinFET cache

inferred← citeshttps://doi.org/10.1145/2966986.2967039openalex-snapshot

Exploring aging deceleration in FinFET-based multi-core systems

inferred← citeshttps://doi.org/10.1145/3528416.3530223openalex-snapshot

STIFF

inferred← citeshttps://doi.org/10.1145/3665276openalex-snapshot

TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores

inferred← citeshttps://doi.org/10.1155/2014/365689openalex-snapshot

FinFETs: From Devices to Architectures

inferred← citeshttps://doi.org/10.1561/1000000031openalex-snapshot

Addressing Process Variations at the Microarchitecture and System Level

inferred← citeshttps://doi.org/10.1587/transinf.2021edp7201openalex-snapshot

A Conflict-Aware Capacity Control Mechanism for Deep Cache Hierarchy

inferred← citeshttps://doi.org/10.23919/date54114.2022.9774647openalex-snapshot

RESTORE: Real-Time Task Scheduling on a Temperature Aware FinFET based Multicore

inferred← citeshttps://doi.org/10.3390/jlpea5030165openalex-snapshot

A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based Cache Memories

inferred← citeshttps://doi.org/10.5555/2755753.2755905openalex-snapshot

Asymmetric underlapped FinFET based robust SRAM design at 7nm node

inferred← citeshttps://doi.org/10.5555/2755753.2757210openalex-snapshot

Memristor based computation-in-memory architecture for data-intensive applications

inferred← citeshttps://doi.org/10.5555/2840819.2840889openalex-snapshot

TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems

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