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Multiple chip planning for chip-interposer codesign

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/aspdac.2011.5722307openalex-snapshot

Row-based area-array I/O design planning in concurrent chip-package design flow

inferredcites →https://doi.org/10.1109/ectc.2008.4550075openalex-snapshot

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

inferredcites →https://doi.org/10.1109/ectc.2011.5898657openalex-snapshot

Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV)

inferredcites →https://doi.org/10.1109/edaps.2010.5683021openalex-snapshot

Area-I/O RDL routing for chip-package codesign considering regional assignment

inferredcites →https://doi.org/10.1109/iccad.2010.5653704openalex-snapshot

Board driven I/O planning & optimization

inferredcites →https://doi.org/10.1109/isqed.2008.4479806openalex-snapshot

An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

inferredcites →https://doi.org/10.1109/tcad.2010.2043586openalex-snapshot

Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews

inferredcites →https://doi.org/10.1109/tvlsi.2009.2017795openalex-snapshot

Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign

inferredcites →https://doi.org/10.1126/science.220.4598.671openalex-snapshot

Optimization by Simulated Annealing

inferredcites →https://doi.org/10.1145/1055137.1055161openalex-snapshot

Modern floorplanning based on fast simulated annealing

inferredcites →https://doi.org/10.1145/1118299.1118356openalex-snapshot

Constraint driven I/O planning and placement for chip-package co-design

inferredcites →https://doi.org/10.1145/1118299.1118357openalex-snapshot

Simultaneous block and I/O buffer floorplanning for flip-chip design

inferredcites →https://doi.org/10.1145/1629911.1630002openalex-snapshot

Flip-chip routing with unified area-I/O pad assignments for package-board co-design

inferredcites →https://doi.org/10.1145/1687399.1687524openalex-snapshot

A study of Through-Silicon-Via impact on the 3D stacked IC layout

inferredcites →https://doi.org/10.1145/2024724.2024873openalex-snapshot

An integrated algorithm for 3D-IC TSV assignment

inferredcites →https://doi.org/10.1145/2228360.2228557openalex-snapshot

A chip-package-board co-design methodology

inferredcites →https://doi.org/10.1145/309847.309928openalex-snapshot

An O-tree representation of non-slicing floorplan and its applications

inferredcites →https://doi.org/10.1145/337292.337541openalex-snapshot

B*-Trees

inferredcites →https://doi.org/10.5555/1509456.1509571openalex-snapshot

Routing for chip-package-board co-design considering differential pairs

inferredcites →https://doi.org/10.5555/1509456.1509572openalex-snapshot

Area-I/O flip-chip routing for chip-package co-design

inferredcites →https://doi.org/10.5555/1950815.1950973openalex-snapshot

Row-based area-array I/O design planning in concurrent chip-package design flow

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.5281/zenodo.3632449openalex-extracted

Design Methodologies and Co-Design Options for Novel 3D Technologies

inferred← citeshttps://doi.org/10.1007/978-3-030-73445-9_3openalex-snapshot

Defenses Against Design Constraint Based Attacks

inferred← citeshttps://doi.org/10.1007/978-3-319-49019-9_12openalex-snapshot

3D/2.5D IC-Based Obfuscation

inferred← citeshttps://doi.org/10.1007/s11227-019-02964-wopenalex-snapshot

Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip

inferred← citeshttps://doi.org/10.1016/j.engappai.2024.109876openalex-snapshot

Optimization of Built-In Self-Test test chain configuration in 2.5D Integrated Circuits Using Constrained Multi-Objective Evolutionary Algorithm

inferred← citeshttps://doi.org/10.1016/j.vlsi.2020.02.006openalex-snapshot

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

inferred← citeshttps://doi.org/10.1109/asp-dac47756.2020.9045359openalex-snapshot

Unified Redistribution Layer Routing for 2.5D IC Packages

inferred← citeshttps://doi.org/10.1109/aspdac.2015.7059009openalex-snapshot

IR to routing challenge and solution for interposer-based design

inferred← citeshttps://doi.org/10.1109/aspdac.2018.8297375openalex-snapshot

Optimal die placement for interposer-based 3D ICs

inferred← citeshttps://doi.org/10.1109/eptc67330.2025.11392651openalex-snapshot

TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning

inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323609openalex-snapshot

Floorplanning for Embedded Multi-Die Interconnect Bridge Packages

inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240755openalex-snapshot

MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package Integration

inferred← citeshttps://doi.org/10.1109/icept.2015.7236746openalex-snapshot

The development of 3D aerospace SRAM integration technology using silicon interposer

inferred← citeshttps://doi.org/10.1109/icept.2015.7236785openalex-snapshot

Study on electrical performance of stacking die package with silicon interposer

inferred← citeshttps://doi.org/10.1109/isqed.2015.7085480openalex-snapshot

Automatic die placement and flexible I/O assignment in 2.5D IC design

inferred← citeshttps://doi.org/10.1109/mtv.2016.17openalex-snapshot

2.5D/3D Integration Technologies for Circuit Obfuscation

inferred← citeshttps://doi.org/10.1109/tcad.2016.2611515openalex-snapshot

ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles

inferred← citeshttps://doi.org/10.1109/tcsi.2022.3200410openalex-snapshot

Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination

inferred← citeshttps://doi.org/10.1109/tvlsi.2021.3113918openalex-snapshot

Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs

inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3291381openalex-snapshot

Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package

inferred← citeshttps://doi.org/10.1109/vts.2015.7116266openalex-snapshot

ExTest scheduling for 2.5D system-on-chip integrated circuits

inferred← citeshttps://doi.org/10.1145/2593069.2593142openalex-snapshot

Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs

inferred← citeshttps://doi.org/10.1145/2808414.2808420openalex-snapshot

Security-Aware Design Flow for 2.5D IC Technology

inferred← citeshttps://doi.org/10.1145/2902961.2903025openalex-snapshot

Modular Placement for Interposer based Multi-FPGA Systems

inferred← citeshttps://doi.org/10.1145/3400302.3415767openalex-snapshot

Intelligent design automation for 2.5/3D heterogeneous SoC integration

inferred← citeshttps://doi.org/10.1145/3569052.3578917openalex-snapshot

Automated Design of Chiplets

inferred← citeshttps://doi.org/10.1145/3626184.3639690openalex-snapshot

Physical Design Challenges in Modern Heterogeneous Integration

inferred← citeshttps://doi.org/10.1145/3676536.3676648openalex-snapshot

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC

inferred← citeshttps://doi.org/10.1145/3716893openalex-snapshot

Thermal-Aware Chiplet Placement for 2.5D ICs with Sequence Pair Based Tree

inferred← citeshttps://doi.org/10.1587/transfun.2019kep0015openalex-snapshot

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections

inferred← citeshttps://doi.org/10.1587/transfun.e98.a.2565openalex-snapshot

A Length Matching Routing Algorithm for Set-Pair Routing Problem

inferred← citeshttps://doi.org/10.2197/ipsjtsldm.10.45openalex-snapshot

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

inferred← citeshttps://doi.org/10.2991/icmemtc-16.2016.317openalex-snapshot

Study on Electrical Performance of FC and WB in IC Ceramic Package

inferred← citeshttps://doi.org/10.32657/10356/73042openalex-snapshot

Design automation flow for partial run-time reconfiguration on FPGAs

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