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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-63465-7_226openalex-snapshot
VPR: a new packing, placement and routing tool for FPGA research
inferredcites →https://doi.org/10.1007/978-3-540-68279-0_2openalex-snapshot
The Hungarian Method for the Assignment Problem
inferredcites →https://doi.org/10.1007/978-3-540-70592-5_5openalex-snapshot
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
inferredcites →https://doi.org/10.1109/asap.2011.6043237openalex-snapshot
Low-cost hardware profiling of run-time and energy in FPGA embedded processors
inferredcites →https://doi.org/10.1109/fccm.2009.24openalex-snapshot
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy
inferredcites →https://doi.org/10.1109/fccm.2010.28openalex-snapshot
Designing Modular Hardware Accelerators in C with ROCCC 2.0
inferredcites →https://doi.org/10.1109/fpl.2008.4629927openalex-snapshot
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures
inferredcites →https://doi.org/10.1109/mc.2003.1231200openalex-snapshot
Embedded computing - Closing the soc design gap
inferredcites →https://doi.org/10.1109/mc.2007.107openalex-snapshot
Trident: From High-Level Language to Hardware Circuitry
inferredcites →https://doi.org/10.1109/mc.2008.240openalex-snapshot
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits
inferredcites →https://doi.org/10.1109/mdt.2009.69openalex-snapshot
An Introduction to High-Level Synthesis
inferredcites →https://doi.org/10.1109/reconfig.2008.57openalex-snapshot
Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs
inferredcites →https://doi.org/10.1109/socc.2006.283880openalex-snapshot
Platform-Based Behavior-Level and System-Level Synthesis
inferredcites →https://doi.org/10.1109/tcad.2003.822133openalex-snapshot
Custom-Instruction Synthesis for Extensible-Processor Platforms
inferredcites →https://doi.org/10.1109/tcad.2005.855950openalex-snapshot
Exact and approximate algorithms for the extension of embedded processor instruction sets
inferredcites →https://doi.org/10.1145/1146909.1147025openalex-snapshot
An efficient and versatile scheduling algorithm based on SDC formulation
inferredcites →https://doi.org/10.1145/1146909.1147048openalex-snapshot
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
inferredcites →https://doi.org/10.1145/123186.123350openalex-snapshot
Data path allocation based on bipartite weighted matching
inferredcites →https://doi.org/10.1145/1575774.1575776openalex-snapshot
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation
inferredcites →https://doi.org/10.2197/ipsjjip.17.242openalex-snapshot
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis
inferredcites →https://doi.org/10.5555/1015090.1015109openalex-snapshot
Register binding and port assignment for multiplexer optimization
inferredcites →https://doi.org/10.5555/1899721.1899885openalex-snapshot
A high-level synthesis flow for custom instruction set extensions for application-specific processors
inferredcites →https://doi.org/10.5860/choice.39sup-0462openalex-snapshot
Occupational outlook handbook, 2002-03 edition
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119813873.ch3openalex-snapshot
High‐Level Synthesis ( HLS )
inferred← citeshttps://doi.org/10.1007/978-3-030-02807-7_2openalex-snapshot
Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework
inferred← citeshttps://doi.org/10.1007/978-3-030-17227-5_17openalex-snapshot
Graph-Based Code Restructuring Targeting HLS for FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-030-44534-8_4openalex-snapshot
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems
inferred← citeshttps://doi.org/10.1007/978-3-030-53532-2_2openalex-snapshot
TRP: A Foundational Platform for High-Performance Low-Power Embedded Image Processing
inferred← citeshttps://doi.org/10.1007/978-3-030-53532-2_5openalex-snapshot
STHEM: Productive Implementation of High-Performance Embedded Image Processing Applications
inferred← citeshttps://doi.org/10.1007/978-3-030-78841-4_13openalex-snapshot
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage
inferred← citeshttps://doi.org/10.1007/978-3-030-78841-4_15openalex-snapshot
Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits
inferred← citeshttps://doi.org/10.1007/978-3-031-04580-6_16openalex-snapshot
Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-031-13074-8_18openalex-snapshot
ML for System-Level Modeling
inferred← citeshttps://doi.org/10.1007/978-3-031-39932-9_3openalex-snapshot
Compilation and Optimizations for Efficient Machine Learning on Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-78377-7_17openalex-snapshot
NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-78380-7_7openalex-snapshot
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-319-26408-0_14openalex-snapshot
The LEAP FPGA Operating System
inferred← citeshttps://doi.org/10.1007/978-3-319-26408-0_3openalex-snapshot
A Quick Tour of High-Level Synthesis Solutions for FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-319-26408-0_7openalex-snapshot
Big Data and HPC Acceleration with Vivado HLS
inferred← citeshttps://doi.org/10.1007/978-3-319-30481-6_2openalex-snapshot
A Design Methodology for the Next Generation Real-Time Vision Processors
inferred← citeshttps://doi.org/10.1007/978-3-319-31723-6_4openalex-snapshot
A Special-Purpose Language for Implementing Pipelined FPGA-Based Accelerators
inferred← citeshttps://doi.org/10.1007/978-3-319-56258-2_12openalex-snapshot
A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures
inferred← citeshttps://doi.org/10.1007/978-3-319-92792-3_4openalex-snapshot
The Green Computing Continuum: The OPERA Perspective
inferred← citeshttps://doi.org/10.1007/978-981-10-5828-8_61openalex-snapshot
A Study of Memory Access Patterns as an Indicator of Performance in High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_19-1openalex-snapshot
Accelerator Design with High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/978-981-95-3643-6_3openalex-snapshot
Sequential Equivalence Checking for Specialized IR via Instrumentation-Based Symbolic Execution
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_19openalex-snapshot
Accelerator Design with High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/s11265-017-1230-1openalex-snapshot
An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
inferred← citeshttps://doi.org/10.1007/s11265-020-01519-0openalex-snapshot
Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
inferred← citeshttps://doi.org/10.1007/s11277-017-5211-2openalex-snapshot
Design of Target Recognition System Based on Machine Learning Hardware Accelerator
inferred← citeshttps://doi.org/10.1007/s11390-020-9414-8openalex-snapshot
A Survey on Performance Optimization of High-Level Synthesis Tools
inferred← citeshttps://doi.org/10.1016/b978-0-12-804189-5.00007-7openalex-snapshot
Targeting heterogeneous computing platforms
inferred← citeshttps://doi.org/10.1016/j.amc.2015.07.042openalex-snapshot
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis
inferred← citeshttps://doi.org/10.1016/j.comcom.2018.07.012openalex-snapshot
Software-defined Radios: Architecture, state-of-the-art, and challenges
inferred← citeshttps://doi.org/10.1016/j.eswa.2014.01.041openalex-snapshot
Automated exploration of datapath and unrolling factor during power–performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm
inferred← citeshttps://doi.org/10.1016/j.future.2020.03.061openalex-snapshot
Architecturally truly diverse systems: A review
inferred← citeshttps://doi.org/10.1016/j.jpdc.2021.10.009openalex-snapshot
A hardware/software co-design methodology for in-memory processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2019.102909openalex-snapshot
LLVM-based automation of memory decoupling for OpenCL applications on FPGAs
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104334openalex-snapshot
Non-iterative SDC modulo scheduling for high-level synthesis
inferred← citeshttps://doi.org/10.1016/j.microrel.2018.06.016openalex-snapshot
Lifetime-aware scheduling in high level synthesis
inferred← citeshttps://doi.org/10.1016/j.microrel.2019.113549openalex-snapshot
Aging-aware scheduling and binding in high-level synthesis considering workload effects
inferred← citeshttps://doi.org/10.1016/j.microrel.2021.114226openalex-snapshot
PReCEP: Automatic insertion of Partial Redundancy based on Critical Error Probability
inferred← citeshttps://doi.org/10.1016/j.seta.2023.103201openalex-snapshot
High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation
inferred← citeshttps://doi.org/10.1016/j.sysarc.2019.01.007openalex-snapshot
A Survey and Taxonomy of FPGA-based Deep Learning Accelerators
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103211openalex-snapshot
Expanding hardware accelerator system design space exploration with gem5-SALAMv2
inferred← citeshttps://doi.org/10.1016/j.vlsi.2016.11.006openalex-snapshot
New advances of high-level synthesis for efficient and reliable hardware design
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.05.001openalex-snapshot
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs
inferred← citeshttps://doi.org/10.1038/s41598-023-48981-xopenalex-snapshot
GAHLS: an optimized graph analytics based high level synthesis framework
inferred← citeshttps://doi.org/10.1088/1361-6579/ada8f0openalex-snapshot
tinyHLS: a novel open source high level synthesis tool targeting hardware accelerators for artificial neural network inference
inferred← citeshttps://doi.org/10.1088/1742-6596/649/1/012001openalex-snapshot
LALPC: Exploiting Parallelism from FPGAs Using C Language
inferred← citeshttps://doi.org/10.1109/access.2019.2911709openalex-snapshot
Low-Power and High-Speed Deep FPGA Inference Engines for Weed Classification at the Edge
inferred← citeshttps://doi.org/10.1109/access.2020.3017552openalex-snapshot
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
inferred← citeshttps://doi.org/10.1109/access.2020.3040081openalex-snapshot
In-FPGA Instrumentation Framework for OpenCL-Based Designs
inferred← citeshttps://doi.org/10.1109/access.2023.3288431openalex-snapshot
A Survey on FPGA-Based Heterogeneous Clusters Architectures
inferred← citeshttps://doi.org/10.1109/access.2024.3450105openalex-snapshot
Beyond Von Neumann Architectures: Exploring Algorithmic Opportunities via Octantis
inferred← citeshttps://doi.org/10.1109/acomp.2015.26openalex-snapshot
Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach
inferred← citeshttps://doi.org/10.1109/acssc.2017.8335150openalex-snapshot
From C to elastic circuits
inferred← citeshttps://doi.org/10.1109/ancs.2013.6665201openalex-snapshot
SWSL: SoftWare Synthesis for network Lookup
inferred← citeshttps://doi.org/10.1109/asap.2013.6567547openalex-snapshot
Modelling communication overhead for accessing local memories in hardware accelerators
inferred← citeshttps://doi.org/10.1109/asap.2016.7760777openalex-snapshot
Synthesisable recursion for C++ HLS tools
inferred← citeshttps://doi.org/10.1109/asap.2017.7995257openalex-snapshot
High-Level Synthesis for side-channel defense
inferred← citeshttps://doi.org/10.1109/asap57973.2023.00037openalex-snapshot
FarSlayer: Turnkey Acceleration of Legacy Software on Commodity FPGA Cards
inferred← citeshttps://doi.org/10.1109/asicon52560.2021.9620230openalex-snapshot
A Practical High-Level Synthesis Framework
inferred← citeshttps://doi.org/10.1109/asicon52560.2021.9620276openalex-snapshot
Highly Efficient Modulo Loop Pipeline For High Level Synthesis
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420433openalex-snapshot
Automatic Recursion Elimination using Recurrence Relations for Synthesis of Stack-free Hardware
inferred← citeshttps://doi.org/10.1109/ccaa.2017.8229944openalex-snapshot
Source-to-source translation: Impact on the performance of high level synthesis
inferred← citeshttps://doi.org/10.1109/coins65080.2025.11125726openalex-snapshot
TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
inferred← citeshttps://doi.org/10.1109/dsd57027.2022.00019openalex-snapshot
ImageSpec: Efficient High-Level Synthesis of Image Processing Applications
inferred← citeshttps://doi.org/10.1109/dtis53253.2021.9505135openalex-snapshot
Octantis: An Exploration Tool for Beyond von Neumann architectures
inferred← citeshttps://doi.org/10.1109/ets.2015.7138739openalex-snapshot
Reliability-aware operation chaining in high level synthesis
inferred← citeshttps://doi.org/10.1109/euc.2014.26openalex-snapshot
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/euc.2015.23openalex-snapshot
Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC
inferred← citeshttps://doi.org/10.1109/ewdts52692.2021.9580996openalex-snapshot
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery
inferred← citeshttps://doi.org/10.1109/fccm.2015.22openalex-snapshot
An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures
inferred← citeshttps://doi.org/10.1109/fccm.2015.25openalex-snapshot
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs
inferred← citeshttps://doi.org/10.1109/fccm.2017.29openalex-snapshot
Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices
inferred← citeshttps://doi.org/10.1109/fccm.2017.33openalex-snapshot
Using Runahead Execution to Hide Memory Latency in High Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm.2017.57openalex-snapshot
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS
inferred← citeshttps://doi.org/10.1109/fccm.2018.00046openalex-snapshot
From C to Fault-Tolerant FPGA-Based Systems
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00031openalex-snapshot
Probabilistic Scheduling in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00034openalex-snapshot
An Empirical Study of the Reliability of High-Level Synthesis Tools
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786084openalex-snapshot
Resource Sharing in Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/fpl.2014.6927496openalex-snapshot
Source-level debugging for FPGA high-level synthesis
inferred← citeshttps://doi.org/10.1109/fpl.2014.6927498openalex-snapshot
Effective FPGA debug for high-level synthesis generated circuits
inferred← citeshttps://doi.org/10.1109/fpl.2015.7293958openalex-snapshot
Inter-procedural resource sharing in High Level Synthesis through function proxies
inferred← citeshttps://doi.org/10.1109/fpl.2015.7294011openalex-snapshot
Automatic support for multi-module parallelism from computational patterns
inferred← citeshttps://doi.org/10.1109/fpl.2015.7294018openalex-snapshot
Scavenger: Automating the construction of application-optimized memory hierarchies
inferred← citeshttps://doi.org/10.1109/fpl.2015.7294024openalex-snapshot
PushPush: Seamless integration of hardware and software objects via function calls over AXI
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577369openalex-snapshot
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577371openalex-snapshot
Quantifying observability for in-system debug of high-level synthesis circuits
inferred← citeshttps://doi.org/10.1109/fpl.2016.7577380openalex-snapshot
Survey of domain-specific languages for FPGA computing
inferred← citeshttps://doi.org/10.1109/fpl.2018.00076openalex-snapshot
An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00045openalex-snapshot
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs
inferred← citeshttps://doi.org/10.1109/fpl50879.2020.00068openalex-snapshot
Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00014openalex-snapshot
DynaRapid: Fast-Tracking from C to Routed Circuits
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718343openalex-snapshot
Bitwidth-optimized hardware accelerators with software fallback
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718424openalex-snapshot
From C to Blokus Duo with LegUp high-level synthesis
inferred← citeshttps://doi.org/10.1109/fpt.2014.7082748openalex-snapshot
Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS
inferred← citeshttps://doi.org/10.1109/fpt.2014.7082758openalex-snapshot
Architectural synthesis of computational pipelines with decoupled memory access
inferred← citeshttps://doi.org/10.1109/fpt.2015.7393128openalex-snapshot
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2016.7929514openalex-snapshot
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs
inferred← citeshttps://doi.org/10.1109/fpt.2016.7929527openalex-snapshot
Enriching C-based High-Level Synthesis with parallel pattern templates
inferred← citeshttps://doi.org/10.1109/fpt.2018.00020openalex-snapshot
Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach
inferred← citeshttps://doi.org/10.1109/fpt.2018.00021openalex-snapshot
Application Acceleration on FPGAs with OmpSs@FPGA
inferred← citeshttps://doi.org/10.1109/fpt.2018.00072openalex-snapshot
Unified On-Chip Software and Hardware Debug for HLS-Accelerated Programs
inferred← citeshttps://doi.org/10.1109/hpcs.2018.00030openalex-snapshot
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis
inferred← citeshttps://doi.org/10.1109/hpcsim.2014.6903758openalex-snapshot
Cyfield-RISP: An OpenCL-generated processor for reconfigurable hardware
inferred← citeshttps://doi.org/10.1109/hpec58863.2023.10363530openalex-snapshot
Improved Models for Policy-Agent Learning of Compiler Directives in HLS
inferred← citeshttps://doi.org/10.1109/iccad.2015.7372552openalex-snapshot
Code transformations based on speculative SDC scheduling
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323639openalex-snapshot
MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323796openalex-snapshot
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753326openalex-snapshot
Towards a timing attack aware high-level synthesis of integrated circuits
inferred← citeshttps://doi.org/10.1109/iccd.2018.00040openalex-snapshot
Lattice-Traversing Design Space Exploration for High Level Synthesis
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00024openalex-snapshot
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00060openalex-snapshot
Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iccic.2016.7919615openalex-snapshot
Open source HLS tools: A stepping stone for modern electronic CAD
inferred← citeshttps://doi.org/10.1109/icetci61221.2024.10594247openalex-snapshot
A Convolutional Neural Network Accelerator with High-level Synthesis
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00031openalex-snapshot
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs
inferred← citeshttps://doi.org/10.1109/icfpt52863.2021.9609930openalex-snapshot
FLOWER: A comprehensive dataflow compiler for high-level synthesis
inferred← citeshttps://doi.org/10.1109/icfpt56656.2022.9974425openalex-snapshot
Load-Store Queue Sizing for Efficient Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/icrc.2017.8123649openalex-snapshot
Generalize or Die: Operating Systems Support for Memristor-Based Accelerators
inferred← citeshttps://doi.org/10.1109/icreed65908.2025.11036219openalex-snapshot
Real-Time Soft Error Mitigation System for SRAM-Based FPGAs
inferred← citeshttps://doi.org/10.1109/icrss57469.2022.00019openalex-snapshot
The Design and Implementation of Complex Float Matrix Multiplication Operation Based on High-level Synthesis
inferred← citeshttps://doi.org/10.1109/igsc54211.2021.9651650openalex-snapshot
Inf4Edge: Automatic Resource-aware Generation of Energy-efficient CNN Inference Accelerator for Edge Embedded FPGAs
inferred← citeshttps://doi.org/10.1109/induscon66435.2025.11241520openalex-snapshot
Open Hardware Synthesis: A Precursor Case Study
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.21openalex-snapshot
Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.31openalex-snapshot
Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration
inferred← citeshttps://doi.org/10.1109/ipdpsw.2014.34openalex-snapshot
High-Level Synthesis from C vs. a DSL-Based Approach
inferred← citeshttps://doi.org/10.1109/ipdpsw.2016.56openalex-snapshot
A Rapid Prototyping Method to Reduce the Design Time in Commercial High-Level Synthesis Tools
inferred← citeshttps://doi.org/10.1109/ipdpsw50202.2020.00020openalex-snapshot
Improving HLS Generated Accelerators Through Relaxed Memory Access Scheduling
inferred← citeshttps://doi.org/10.1109/ipdpsw71298.2026.00053openalex-snapshot
Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach
inferred← citeshttps://doi.org/10.1109/iraniancee.2015.7146300openalex-snapshot
Functional cores: Trade a little performance to save power
inferred← citeshttps://doi.org/10.1109/iraniancee.2019.8786539openalex-snapshot
OMID: Optimized MIcro-Architecture Design for Fog Computing Applications
inferred← citeshttps://doi.org/10.1109/isca.2016.20openalex-snapshot
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181274openalex-snapshot
Using Reduced Graphs for Efficient HLS Scheduling
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937754openalex-snapshot
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401780openalex-snapshot
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
inferred← citeshttps://doi.org/10.1109/islped52811.2021.9502501openalex-snapshot
DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing
inferred← citeshttps://doi.org/10.1109/ismvl49045.2020.00-28openalex-snapshot
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
inferred← citeshttps://doi.org/10.1109/isvdat.2016.8064857openalex-snapshot
An efficient FPGA-based function profiler for embedded system applications
inferred← citeshttps://doi.org/10.1109/isvlsi.2014.10openalex-snapshot
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff
inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00052openalex-snapshot
Low Overhead Online Checkpoint for Intermittently Powered Non-volatile FPGAs
inferred← citeshttps://doi.org/10.1109/isvlsi49217.2020.00016openalex-snapshot
Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/isvlsi51109.2021.00018openalex-snapshot
Reverse Engineering Register to Variable Mapping in High-level Synthesis
inferred← citeshttps://doi.org/10.1109/jproc.2014.2386883openalex-snapshot
Reconfigurable Computing Architectures
inferred← citeshttps://doi.org/10.1109/jproc.2015.2399275openalex-snapshot
High-Level Language Tools for Reconfigurable Computing
inferred← citeshttps://doi.org/10.1109/lca.2016.2615617openalex-snapshot
HeteroSim: A Heterogeneous CPU-FPGA Simulator
inferred← citeshttps://doi.org/10.1109/mcas.2021.3071631openalex-snapshot
Synthesizing General-Purpose Code Into Dynamically Scheduled Circuits
inferred← citeshttps://doi.org/10.1109/mce.2016.2516108openalex-snapshot
Design Flow of a Digital IC: The role of digital IC\/SOC design in CE products
inferred← citeshttps://doi.org/10.1109/meco49872.2020.9134071openalex-snapshot
Strategies of Computational Process Synthesis — a System-Level Model of HW/SW (Micro)Architectural Mechanisms
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00047openalex-snapshot
gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling
inferred← citeshttps://doi.org/10.1109/mm.2021.3088670openalex-snapshot
A Binary Translation Framework for Automated Hardware Generation
inferred← citeshttps://doi.org/10.1109/mwscas.2017.8052932openalex-snapshot
A medium-grained reconfigurable architecture targeting high-level synthesis implementation
inferred← citeshttps://doi.org/10.1109/optim-acemp62776.2025.11075262openalex-snapshot
Design Space Exploration through Architecture Driven High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/patmos.2018.8464170openalex-snapshot
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
inferred← citeshttps://doi.org/10.1109/reconfig.2017.8279778openalex-snapshot
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp
inferred← citeshttps://doi.org/10.1109/reconfig.2017.8279807openalex-snapshot
Rapid circuit-specific inlining tuning for FPGA high-level synthesis
inferred← citeshttps://doi.org/10.1109/reconfig48160.2019.8994693openalex-snapshot
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development
inferred← citeshttps://doi.org/10.1109/reconfig48160.2019.8994778openalex-snapshot
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs
inferred← citeshttps://doi.org/10.1109/recosoc.2016.7533911openalex-snapshot
A programming model for reconfigurable computing based in functional concurrency
inferred← citeshttps://doi.org/10.1109/sbcci62366.2024.10704008openalex-snapshot
Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet Forwarding
inferred← citeshttps://doi.org/10.1109/sbesc53686.2021.9628356openalex-snapshot
Lightweight Dual Modular Redundancy through Approximate Computing
inferred← citeshttps://doi.org/10.1109/scc61854.2024.00013openalex-snapshot
Open-CFR: Open-Source Co-Design Framework for Redundancy with DPR in COTS FPGA SoCs
inferred← citeshttps://doi.org/10.1109/socc.2017.8226056openalex-snapshot
FPGA-based CNN inference accelerator synthesized from multi-threaded C software
inferred← citeshttps://doi.org/10.1109/tc.2021.3066466openalex-snapshot
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code
inferred← citeshttps://doi.org/10.1109/tc.2021.3086106openalex-snapshot
OmpSs@FPGA framework for high performance FPGA computing
inferred← citeshttps://doi.org/10.1109/tc.2023.3292590openalex-snapshot
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets
inferred← citeshttps://doi.org/10.1109/tcad.2015.2445734openalex-snapshot
Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating
inferred← citeshttps://doi.org/10.1109/tcad.2016.2565204openalex-snapshot
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2018.2818689openalex-snapshot
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code
inferred← citeshttps://doi.org/10.1109/tcad.2018.2834440openalex-snapshot
Scaling Up Modulo Scheduling for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2018.2837103openalex-snapshot
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2020.2995342openalex-snapshot
Multistage Multirate Transfer Function Automated Synthesis Using Hybrid Sampling Strategy-Based Differential Evolution
inferred← citeshttps://doi.org/10.1109/tcad.2021.3060320openalex-snapshot
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2021.3090339openalex-snapshot
FastSim: A Fast Simulation Framework for High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tcad.2021.3105574openalex-snapshot
From C/C++ Code to High-Performance Dataflow Circuits
inferred← citeshttps://doi.org/10.1109/tcad.2022.3179323openalex-snapshot
A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs
inferred← citeshttps://doi.org/10.1109/tcad.2023.3246387openalex-snapshot
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
inferred← citeshttps://doi.org/10.1109/tcad.2024.3410154openalex-snapshot
ROVER: RTL Optimization via Verified E-Graph Rewriting
inferred← citeshttps://doi.org/10.1109/tcsi.2023.3299009openalex-snapshot
Generating Posit-Based Accelerators With High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/tetc.2018.2794068openalex-snapshot
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration
inferred← citeshttps://doi.org/10.1109/tmscs.2017.2699647openalex-snapshot
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems
inferred← citeshttps://doi.org/10.1109/tpds.2017.2746081openalex-snapshot
Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA
inferred← citeshttps://doi.org/10.1109/tr.2025.3547739openalex-snapshot
Insights From Bugs in FPGA High-Level Synthesis Tools: An Empirical Study of Bambu Bugs
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2483525openalex-snapshot
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation
inferred← citeshttps://doi.org/10.1109/vlsi-sata.2016.7593046openalex-snapshot
Non-intrusive FPGA-based profiler for loop execution characterization
inferred← citeshttps://doi.org/10.1117/12.3050018openalex-snapshot
Design and simulation of parameter intensive shallow CNN acceleration method based on FPGA
inferred← citeshttps://doi.org/10.1142/s0218126616500298openalex-snapshot
Soft Core Processor Generated Based on the Machine Code of the Application
inferred← citeshttps://doi.org/10.1145/2593069.2593200openalex-snapshot
Reliability-aware Register Binding for Control-Flow Intensive Designs
inferred← citeshttps://doi.org/10.1145/2602988.2602996openalex-snapshot
Parallel real-time garbage collection of multiple heaps in reconfigurable hardware
inferred← citeshttps://doi.org/10.1145/2629547openalex-snapshot
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
inferred← citeshttps://doi.org/10.1145/2684746.2689065openalex-snapshot
Resource-Aware Throughput Optimization for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/2684746.2689089openalex-snapshot
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System
inferred← citeshttps://doi.org/10.1145/2744769.2744851openalex-snapshot
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths
inferred← citeshttps://doi.org/10.1145/2764967.2771935openalex-snapshot
High-level software-pipelining in LLVM
inferred← citeshttps://doi.org/10.1145/2775049.2602996openalex-snapshot
Parallel real-time garbage collection of multiple heaps in reconfigurable hardware
inferred← citeshttps://doi.org/10.1145/2839300openalex-snapshot
Reliability-Aware Resource Allocation and Binding in High-Level Synthesis
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