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Thermal Implications of On-Chip Voltage Regulation
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-0-387-71601-5openalex-snapshot
Power Distribution Networks with On-Chip Decoupling Capacitors
inferredcites →https://doi.org/10.1007/978-1-4419-7871-4openalex-snapshot
Power Distribution Networks with On-Chip Decoupling Capacitors
inferredcites →https://doi.org/10.1007/s10470-012-9841-8openalex-snapshot
A fully on-chip area-efficient CMOS low-dropout regulator with fast load regulation
inferredcites →https://doi.org/10.1016/j.vlsi.2011.12.002openalex-snapshot
Architectural implications of spatial thermal filtering
inferredcites →https://doi.org/10.1109/apec.2013.6520285openalex-snapshot
A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
inferredcites →https://doi.org/10.1109/hpca.2008.4658633openalex-snapshot
System level analysis of fast, per-core DVFS using on-chip switching regulators
inferredcites →https://doi.org/10.1109/isscc.2006.1696279openalex-snapshot
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters
inferredcites →https://doi.org/10.1109/jetcas.2012.2226378openalex-snapshot
Distributed On-Chip Power Delivery
inferredcites →https://doi.org/10.1109/jetcas.2014.2315880openalex-snapshot
Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System
inferredcites →https://doi.org/10.1109/jssc.2006.885041openalex-snapshot
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
inferredcites →https://doi.org/10.1109/jssc.2012.2185354openalex-snapshot
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage
inferredcites →https://doi.org/10.1109/tcsii.2011.2168016openalex-snapshot
Effective Resistance of a Two Layer Mesh
inferredcites →https://doi.org/10.1109/tvlsi.2006.876103openalex-snapshot
HotSpot: a compact thermal modeling methodology for early-stage VLSI design
inferredcites →https://doi.org/10.1109/tvlsi.2012.2190539openalex-snapshot
Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation
inferredcites →https://doi.org/10.1145/2024724.2024944openalex-snapshot
Fast algorithms forIRvoltage drop analysis exploiting locality
inferredcites →https://doi.org/10.1145/2187671.2187675openalex-snapshot
Recent thermal management techniques for microprocessors
inferredcites →https://doi.org/10.1145/2429384.2429433openalex-snapshot
Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators
inferredcites →https://doi.org/10.1145/2429384.2429435openalex-snapshot
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications
inferredcites →https://doi.org/10.1587/transele.e94.c.938openalex-snapshot
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.5281/zenodo.1253592openalex-extracted
Hipdn: A Power Distribution Network For Efficient On-Chip Power Delivery And Finegrain Low-Power Applications
inferred← citeshttps://doi.org/10.1007/978-3-030-53273-4_9openalex-snapshot
Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance
inferred← citeshttps://doi.org/10.1109/eit.2019.8833756openalex-snapshot
Voltage Regulator Thermal Matrix based Thread Allocation Optimization for a Multi-Core Processor
inferred← citeshttps://doi.org/10.1109/icdsp.2018.8631825openalex-snapshot
When Hardware Security Moves to the Edge and Fog
inferred← citeshttps://doi.org/10.1109/jetcas.2014.2315880openalex-snapshot
Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System
inferred← citeshttps://doi.org/10.1109/natw.2019.8758751openalex-snapshot
Convolutional Neural Networks (CNNs)-Assisted Voltage Regulation: A New Power Delivery Scheme
inferred← citeshttps://doi.org/10.1109/tcpmt.2021.3124248openalex-snapshot
Multiphysics Challenges and Opportunities for Integrated Voltage Regulators in Power Delivery Architectures
inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2871381openalex-snapshot
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation
inferred← citeshttps://doi.org/10.1145/3194554.3194602openalex-snapshot
Reliable On-Chip Voltage Regulation for Sustainable and Compact IoT and Heterogeneous Computing Systems
inferred← citeshttps://doi.org/10.23919/date.2018.8342116openalex-snapshot
Mitigation of NBTI induced performance degradation in on-chip digital LDOs
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