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Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/sat.787openalex-snapshot
DVB‐S2 low density parity check codes with near Shannon limit performance
inferredcites →https://doi.org/10.1007/978-1-4020-8588-8openalex-snapshot
High-Level Synthesis: from Algorithm to Digital Circuit
inferredcites →https://doi.org/10.1007/b101872openalex-snapshot
Fundamentals of Codes, Graphs, and Iterative Decoding
inferredcites →https://doi.org/10.1016/s0165-1684(03)00090-2openalex-snapshot
Rapid prototyping for wireless designs: the five-ones approach
inferredcites →https://doi.org/10.1049/el.2011.0201openalex-snapshot
GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection
inferredcites →https://doi.org/10.1109/fccm.2011.19openalex-snapshot
Synthesis of Platform Architectures from OpenCL Programs
inferredcites →https://doi.org/10.1109/fccm.2011.31openalex-snapshot
Using Functional Programming to Generate an LDPC Forward Error Corrector
inferredcites →https://doi.org/10.1109/fpl.2010.93openalex-snapshot
OpenRCL: Low-Power High-Performance Computing with Reconfigurable Devices
inferredcites →https://doi.org/10.1109/iscas.2012.6272149openalex-snapshot
Transpose-free SAR imaging on FPGA platform
inferredcites →https://doi.org/10.1109/jlt.2011.2175479openalex-snapshot
Staircase Codes: FEC for 100 Gb/s OTN
inferredcites →https://doi.org/10.1109/mc.2002.1033026openalex-snapshot
PICO: automatically designing custom computers
inferredcites →https://doi.org/10.1109/msp.2012.2192212openalex-snapshot
Portable LDPC Decoding on Multicores Using OpenCL [Applications Corner]
inferredcites →https://doi.org/10.1109/pact.1996.554030openalex-snapshot
Swing Modulo Scheduling: A Lifetime-Sensitive Approach
inferredcites →https://doi.org/10.1109/pact.2002.1105967openalex-snapshot
Proceedings 2002 International Conference on Parallel Architectures and Compilation Techniques. PACT 2002
inferredcites →https://doi.org/10.1109/sasp.2009.5226333openalex-snapshot
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
inferredcites →https://doi.org/10.1109/tc.2009.179openalex-snapshot
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study
inferredcites →https://doi.org/10.1109/tit.1962.1057683openalex-snapshot
Low-density parity-check codes
inferredcites →https://doi.org/10.1109/tpds.2010.125openalex-snapshot
Comparing Hardware Accelerators in Scientific Applications: A Case Study
inferredcites →https://doi.org/10.1145/288548openalex-snapshot
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98
inferredcites →https://doi.org/10.1145/349299.349317openalex-snapshot
Bidwidth analysis with application to silicon compilation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.7909openalex-snapshot
A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units
inferred← citeshttps://doi.org/10.1007/978-3-031-31209-0_11openalex-snapshot
Modeling Task Mapping for Data-Intensive Applications in Heterogeneous Systems
inferred← citeshttps://doi.org/10.1007/s11063-015-9430-9openalex-snapshot
Stacked Autoencoders Using Low-Power Accelerated Architectures for Object Recognition in Autonomous Systems
inferred← citeshttps://doi.org/10.1007/s11265-020-01519-0openalex-snapshot
Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA Devices
inferred← citeshttps://doi.org/10.1007/s42405-025-01016-3openalex-snapshot
Firmware Updating Approach for FPGA-Based SDR Nanosatellite Payload
inferred← citeshttps://doi.org/10.1016/j.comcom.2018.07.012openalex-snapshot
Software-defined Radios: Architecture, state-of-the-art, and challenges
inferred← citeshttps://doi.org/10.1109/access.2017.2727221openalex-snapshot
Design Space Exploration of LDPC Decoders Using High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/hpcs48598.2019.9188052openalex-snapshot
Design Space Exploration of Embedded Applications on Heterogeneous CPU-GPU Platforms
inferred← citeshttps://doi.org/10.1109/icecs.2018.8617957openalex-snapshot
From multicore LDPC decoder implementations to FPGA decoder architectures: a case study
inferred← citeshttps://doi.org/10.1109/reconfig48160.2019.8994785openalex-snapshot
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes
inferred← citeshttps://doi.org/10.3390/s22124318openalex-snapshot
Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs
inferred← citeshttps://doi.org/10.70675/8a208990zf0a8z43dfza529zb4ca24df8a83openalex-snapshot
Conception et prototypage de décodeurs de codes correcteurs d’erreurs à partir de modèles comportementaux
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