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Synthesizing Optimal Switching Lattices

https://doi.org/10.1145/2661632
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/0-387-27705-6_14openalex-snapshot
Molecular and Nanoscale Computing and Technology
inferredcites →https://doi.org/10.1007/978-1-4613-2821-6openalex-snapshot
Logic Minimization Algorithms for VLSI Synthesis
inferredcites →https://doi.org/10.1007/978-3-642-60085-2_17openalex-snapshot
Stable Models and an Alternative Logic Programming Paradigm
inferredcites →https://doi.org/10.1007/s10601-010-9105-0openalex-snapshot
Cardinality Networks: a theoretical and empirical study
inferredcites →https://doi.org/10.1088/0957-4484/14/4/311openalex-snapshot
Nanoscale molecular-switch crossbar circuits
inferredcites →https://doi.org/10.1109/43.402496openalex-snapshot
Asynchronous circuit synthesis with Boolean satisfiability
inferredcites →https://doi.org/10.1109/tc.1972.5009040openalex-snapshot
A Rectangular Logic Array
inferredcites →https://doi.org/10.1109/tc.2011.170openalex-snapshot
Logic Synthesis for Switching Lattices
inferredcites →https://doi.org/10.1126/science.291.5505.851openalex-snapshot
Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks
inferredcites →https://doi.org/10.1145/1228784.1228812openalex-snapshot
Exact sat-based toffoli network synthesis
inferredcites →https://doi.org/10.1145/2348839.2348848openalex-snapshot
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
inferredcites →https://doi.org/10.1145/2593069.2593135openalex-snapshot
Exact One-pass Synthesis of Digital Microfluidic Biochips
inferredcites →https://doi.org/10.3233/sat190077openalex-snapshot
DepQBF: A Dependency-Aware QBF Solver
inferredcites →https://doi.org/10.5555/1326073.1326120openalex-snapshot
Scalable exploration of functional dependency by interpolation and incremental SAT solving
inferredcites →https://doi.org/10.5555/1326073.1326146openalex-snapshot
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-20323-8_7openalex-snapshot
Literal Selection in Switching Lattice Design
inferred← citeshttps://doi.org/10.1007/978-3-030-23425-6_3openalex-snapshot
The Connection Layout in a Lattice of Four-Terminal Switches
inferred← citeshttps://doi.org/10.1007/s10836-020-05885-2openalex-snapshot
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.08.004openalex-snapshot
Logic synthesis and testing techniques for switching nano-crossbar arrays
inferred← citeshttps://doi.org/10.1016/j.micpro.2017.12.003openalex-snapshot
Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods
inferred← citeshttps://doi.org/10.1016/j.micpro.2018.05.004openalex-snapshot
Composition of switching lattices for regular and for decomposed functions
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.08.002openalex-snapshot
Optimal and heuristic algorithms to synthesize lattices of four-terminal switches
inferred← citeshttps://doi.org/10.1109/dsd.2016.45openalex-snapshot
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer
inferred← citeshttps://doi.org/10.1109/dsd.2016.75openalex-snapshot
Logic Synthesis for Switching Lattices by Decomposition with P-Circuits
inferred← citeshttps://doi.org/10.1109/dsd.2017.54openalex-snapshot
Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis
inferred← citeshttps://doi.org/10.1109/dsd.2019.00054openalex-snapshot
Testability of Switching Lattices in the Cellular Fault Model
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180673openalex-snapshot
A Novel Method for the Realization of Complex Logic Functions using Switching Lattices
inferred← citeshttps://doi.org/10.1109/latw.2019.8704615openalex-snapshot
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model
inferred← citeshttps://doi.org/10.1109/tc.2019.2950663openalex-snapshot
Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
inferred← citeshttps://doi.org/10.1109/tcad.2020.3035629openalex-snapshot
Realization of Logic Functions Using Switching Lattices Under a Delay Constraint
inferred← citeshttps://doi.org/10.1109/tetc.2020.3022426openalex-snapshot
Technology Development and Modeling of Switching Lattices Using Square and H Shaped Four-Terminal Switches
inferred← citeshttps://doi.org/10.1109/tnano.2020.3044017openalex-snapshot
Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2016.7753577openalex-snapshot
Synthesis on switching lattices of Dimension-reducible Boolean functions
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2018.8644806openalex-snapshot
Testability of Switching Lattices in the Stuck at Fault Model
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2018.8644855openalex-snapshot
Two Combinatorial Problems on the Layout of Switching Lattices
inferred← citeshttps://doi.org/10.1145/3232195.3232211openalex-snapshot
Integrated Synthesis Methodology for Crossbar Arrays
inferred← citeshttps://doi.org/10.23919/date.2017.7926998openalex-snapshot
Computing with nano-crossbar arrays: Logic synthesis and fault tolerance
inferred← citeshttps://doi.org/10.23919/date.2019.8714809openalex-snapshot
A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices
inferred← citeshttps://doi.org/10.23919/date.2019.8715123openalex-snapshot
Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116304openalex-snapshot
CMOS Implementation of Switching Lattices
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116566openalex-snapshot
Nano-Crossbar based Computing: Lessons Learned and Future Directions
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