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fpgaConvNet

https://doi.org/10.1145/3020078.3021791
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inferred← citeshttps://doi.org/10.5281/zenodo.5680908openalex-extracted
fastmachinelearning/hls4ml: coris
inferred← citeshttps://doi.org/10.1002/9781119507369.ch3openalex-snapshot
Artificial Neural Networks in Hardware
inferred← citeshttps://doi.org/10.1007/978-3-030-94191-8_80openalex-snapshot
Generic Automated Implementation of Deep Neural Networks on Field Programmable Gate Arrays
inferred← citeshttps://doi.org/10.1007/978-3-032-25032-2_5openalex-snapshot
Exploring the Usability and Applicability of Proof of Learning in Binary Neural Networks
inferred← citeshttps://doi.org/10.1007/s10489-021-02794-5openalex-snapshot
Evaluating performance of AI operators using roofline model
inferred← citeshttps://doi.org/10.1007/s42486-021-00070-6openalex-snapshot
Elastic AI: system support for adaptive machine learning in pervasive computing systems
inferred← citeshttps://doi.org/10.1016/j.neucom.2021.05.069openalex-snapshot
A generic FPGA-based hardware architecture for recursive least mean p-power extreme learning machine
inferred← citeshttps://doi.org/10.1038/s42256-021-00356-5openalex-snapshot
Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors
inferred← citeshttps://doi.org/10.1088/1748-0221/13/07/p07027openalex-snapshot
Fast inference of deep neural networks in FPGAs for particle physics
inferred← citeshttps://doi.org/10.1109/access.2022.3201107openalex-snapshot
High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
inferred← citeshttps://doi.org/10.1109/asap.2018.8445088openalex-snapshot
Hardware Compilation of Deep Neural Networks: An Overview
inferred← citeshttps://doi.org/10.1109/dicct61038.2024.10533053openalex-snapshot
FPGAs as Hardware Accelerators in Data Centers: A Survey From the Data Centric Perspective
inferred← citeshttps://doi.org/10.1109/naecon70028.2026.11674999openalex-snapshot
A Tiled Multi-Layer Systolic Array for FPGA-Based Neural Network Acceleration
inferred← citeshttps://doi.org/10.1109/socc52499.2021.9739550openalex-snapshot
Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAs
inferred← citeshttps://doi.org/10.1109/tc.2020.3033730openalex-snapshot
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs
inferred← citeshttps://doi.org/10.1145/3186332openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs
inferred← citeshttps://doi.org/10.1145/3289185openalex-snapshot
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
inferred← citeshttps://doi.org/10.1145/3289602.3293925openalex-snapshot
Compute-Efficient Neural-Network Acceleration
inferred← citeshttps://doi.org/10.1145/3301278openalex-snapshot
Synergy
inferred← citeshttps://doi.org/10.1145/3453688.3461485openalex-snapshot
DeepDive
inferred← citeshttps://doi.org/10.1145/3454127.3456597openalex-snapshot
DNN2FPGA: Generic Design Flow to Implement DNNs on FPGAs
inferred← citeshttps://doi.org/10.1145/3461648.3463848openalex-snapshot
Optimus: towards optimal layer-fusion on deep learning processors
inferred← citeshttps://doi.org/10.1145/3519598openalex-snapshot
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism
inferred← citeshttps://doi.org/10.1145/3520142openalex-snapshot
Optimus: An Operator Fusion Framework for Deep Neural Networks
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546621openalex-snapshot
Auto WS: Automate Weights Streaming in Layer-Wise Pipelined DNN Accelerators
inferred← citeshttps://doi.org/10.3390/a12080154openalex-snapshot
A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing
inferred← citeshttps://doi.org/10.3390/computers15040219openalex-snapshot
Energy-Efficient Dual-Core RISC-V Architecture for Edge AI Acceleration with Dynamic MAC Unit Reuse
inferred← citeshttps://doi.org/10.3390/electronics14203993openalex-snapshot
Optimized Implementation of YOLOv3-Tiny for Real-Time Image and Video Recognition on FPGA
inferred← citeshttps://doi.org/10.3390/electronics15163536openalex-snapshot
Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs
inferred← citeshttps://doi.org/10.3390/electronics8111321openalex-snapshot
Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning
inferred← citeshttps://doi.org/10.3390/mi14050897openalex-snapshot
A Review of Artificial Intelligence in Embedded Systems
inferred← citeshttps://doi.org/10.3390/s20102828openalex-snapshot
Real-Time Energy Efficient Hand Pose Estimation: A Case Study
inferred← citeshttps://doi.org/10.48550/arxiv.1803.05900openalex-snapshot
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
inferred← citeshttps://doi.org/10.48550/arxiv.1806.08616openalex-snapshot
Deploying Deep Neural Networks in the Embedded Space
inferred← citeshttps://doi.org/10.48550/arxiv.2007.09490openalex-snapshot
DeepDive: An Integrative Algorithm/Architecture Co-Design for Deep Separable Convolutional Neural Networks
inferred← citeshttps://doi.org/10.70675/9b86665cz79bbz400fz9d0bz69433c967981openalex-snapshot
Efficient CNN inference acceleration on FPGAs : a pattern pruning-driven approach
inferred← citeshttps://doi.org/10.70675/b08b2f98z66c2z46d7za694z241b7296cbd2openalex-snapshot
Inference acceleration and optimization in deep neural networks for computer vision
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