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Software challenges for the changing storage landscape

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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-14681-7_1openalex-snapshot
Orthogonal Persistence Revisited
inferredcites →https://doi.org/10.1007/bf01231642openalex-snapshot
Orthogonally persistent object systems
inferredcites →https://doi.org/10.1007/bf01231646openalex-snapshot
Adaptable pointer swizzling strategies in object bases: design, realization, and quantitative analysis
inferredcites →https://doi.org/10.1109/comswa.2006.1665153openalex-snapshot
A Measurement Study of the Linux TCP/IP Stack Performance and Scalability on SMP systems
inferredcites →https://doi.org/10.1109/icpp.1998.708530openalex-snapshot
Efficient sleep/wake-up protocols for user-level IPC
inferredcites →https://doi.org/10.1109/icpp.2000.876064openalex-snapshot
Proceedings of the 2000 International Conference on Parallel Processing
inferredcites →https://doi.org/10.1145/1837210.1837214openalex-snapshot
Exploiting multicore systems with Cilk
inferredcites →https://doi.org/10.1145/1950365.1950379openalex-snapshot
Mnemosyne
inferredcites →https://doi.org/10.1145/1950365.1950380openalex-snapshot
NV-Heaps
inferredcites →https://doi.org/10.1145/1961295.1950379openalex-snapshot
Mnemosyne
inferredcites →https://doi.org/10.1145/1961295.1950380openalex-snapshot
NV-Heaps
inferredcites →https://doi.org/10.1145/2485732.2485740openalex-snapshot
Linux block IO
inferredcites →https://doi.org/10.1145/2872362.2872401openalex-snapshot
memif
inferredcites →https://doi.org/10.1145/2901318.2901325openalex-snapshot
pVM
inferredcites →https://doi.org/10.1145/3037697.3037732openalex-snapshot
ReFlex
inferredcites →https://doi.org/10.1535/itj.1003.02openalex-snapshot
IntelŴVirtualization Technology for Directed I/O
inferredcites →https://doi.org/10.5555/2685048.2685053openalex-snapshot
IX: a protected dataplane operating system for high throughput and low latency

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/s11432-019-9860-1openalex-snapshot
Software system research in post-Moore’s Law era: a historical perspective for the future
inferred← citeshttps://doi.org/10.1007/s42979-019-0057-1openalex-snapshot
Practical Performance Evaluation of Space Optimal Erasure Codes for High-Speed Data Storage Systems
inferred← citeshttps://doi.org/10.1007/s42979-020-00141-yopenalex-snapshot
A New Decoding Algorithm for XOR-Based Erasure Codes
inferred← citeshttps://doi.org/10.1109/hipc.2019.00051openalex-snapshot
uMMAP-IO: User-Level Memory-Mapped I/O for HPC
inferred← citeshttps://doi.org/10.1109/icde55515.2023.00299openalex-snapshot
Nested Loops Revisited Again
inferred← citeshttps://doi.org/10.1109/tcad.2020.3012322openalex-snapshot
When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?
inferred← citeshttps://doi.org/10.1109/tcad.2022.3197517openalex-snapshot
Exploring Synchronous Page Fault Handling
inferred← citeshttps://doi.org/10.1145/3318265.3318272openalex-snapshot
Userland CO-PAGER
inferred← citeshttps://doi.org/10.1145/3343737.3343742openalex-snapshot
ExtOS
inferred← citeshttps://doi.org/10.1145/3508352.3549408openalex-snapshot
GraphRC
inferred← citeshttps://doi.org/10.1145/3613424.3623772openalex-snapshot
Persistent Processor Architecture
inferred← citeshttps://doi.org/10.1145/3649329.3655929openalex-snapshot
How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising
inferred← citeshttps://doi.org/10.14778/3538598.3538612openalex-snapshot
Your read is our priority in flash storage
inferred← citeshttps://doi.org/10.31114/2078-7707-2020-2-158-164openalex-snapshot
Modification of the High Bandwidth Solid State Drive Controller within the multi-stage architecture
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