On the public citation graph
FINN- R
0 signed · 480 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-46493-0_32openalex-snapshot
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
inferredcites →https://doi.org/10.1016/j.neucom.2010.03.021openalex-snapshot
Artificial neural networks in hardware: A survey of two decades of progress
inferredcites →https://doi.org/10.1016/j.neucom.2017.09.046openalex-snapshot
FP-BNN: Binarized neural network on FPGA
inferredcites →https://doi.org/10.1073/pnas.1604850113openalex-snapshot
Convolutional networks for fast, energy-efficient neuromorphic computing
inferredcites →https://doi.org/10.1109/fccm.2016.22openalex-snapshot
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
inferredcites →https://doi.org/10.1109/icassp.2016.7471828openalex-snapshot
FPGA based implementation of deep neural networks using on-chip memory only
inferredcites →https://doi.org/10.1109/ijcnn.2017.7966166openalex-snapshot
Ternary neural networks for resource-efficient AI applications
inferredcites →https://doi.org/10.1109/ipdpsw.2018.00032openalex-snapshot
Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
inferredcites →https://doi.org/10.1109/isca.2016.32openalex-snapshot
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators
inferredcites →https://doi.org/10.1109/isca.2016.40openalex-snapshot
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks
inferredcites →https://doi.org/10.1109/isscc.2014.6757323openalex-snapshot
1.1 Computing's energy problem (and what we can do about it)
inferredcites →https://doi.org/10.1109/les.2017.2743247openalex-snapshot
Tactics to Directly Map CNN Graphs on Embedded FPGAs
inferredcites →https://doi.org/10.1145/2684746.2689060openalex-snapshot
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3020078.3021698openalex-snapshot
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network
inferredcites →https://doi.org/10.1145/3020078.3021736openalex-snapshot
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks
inferredcites →https://doi.org/10.1145/3020078.3021738openalex-snapshot
An OpenCL™ Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.1145/3020078.3021740openalex-snapshot
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?
inferredcites →https://doi.org/10.1145/3020078.3021741openalex-snapshot
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs
inferredcites →https://doi.org/10.1145/3029580.3029586openalex-snapshot
Scaling Binarized Neural Networks on Reconfigurable Logic
inferredcites →https://doi.org/10.1145/3061639.3062207openalex-snapshot
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
inferredcites →https://doi.org/10.1145/3079856.3080246openalex-snapshot
In-Datacenter Performance Analysis of a Tensor Processing Unit
inferredcites →https://doi.org/10.23919/fpl.2017.8056820openalex-snapshot
Accelerating low bit-width convolutional neural networks with embedded FPGA
inferredcites →https://doi.org/10.23919/fpl.2017.8056834openalex-snapshot
Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs
inferredcites →https://doi.org/10.48550/arxiv.1409.1556openalex-snapshot
Very Deep Convolutional Networks for Large-Scale Image Recognition
inferredcites →https://doi.org/10.48550/arxiv.1506.02626openalex-snapshot
Learning both Weights and Connections for Efficient Neural Networks
inferredcites →https://doi.org/10.48550/arxiv.1510.00149openalex-snapshot
Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding
inferredcites →https://doi.org/10.48550/arxiv.1511.06488openalex-snapshot
Resiliency of Deep Neural Networks under Quantization
inferredcites →https://doi.org/10.48550/arxiv.1602.07360openalex-snapshot
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size
inferredcites →https://doi.org/10.48550/arxiv.1603.04467openalex-snapshot
TensorFlow: Large-Scale Machine Learning on Heterogeneous Distributed Systems
inferredcites →https://doi.org/10.48550/arxiv.1606.06160openalex-snapshot
DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
inferredcites →https://doi.org/10.48550/arxiv.1612.01064openalex-snapshot
Trained Ternary Quantization
inferredcites →https://doi.org/10.48550/arxiv.1701.03534openalex-snapshot
An OpenCL(TM) Deep Learning Accelerator on Arria 10
inferredcites →https://doi.org/10.48550/arxiv.1709.01134openalex-snapshot
WRPN: Wide Reduced-Precision Networks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-18338-7_12openalex-snapshot
Digital Neural Network Accelerators
inferred← citeshttps://doi.org/10.1007/978-3-030-44534-8_10openalex-snapshot
Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs
inferred← citeshttps://doi.org/10.1007/978-3-030-81523-3_4openalex-snapshot
Exploration of Hardware Acceleration Methods for an XNOR Traffic Signs Classifier
inferred← citeshttps://doi.org/10.1007/978-3-030-81645-2_9openalex-snapshot
Towards Real-Time Deep Learning-Based Network Intrusion Detection on FPGA
inferred← citeshttps://doi.org/10.1007/978-3-030-86702-7_38openalex-snapshot
Improvement of Visual Perception in Humanoid Robots Using Heterogeneous Architectures for Autonomous Applications
inferred← citeshttps://doi.org/10.1007/978-3-030-95085-9_13openalex-snapshot
SoK - Network Intrusion Detection on FPGA
inferred← citeshttps://doi.org/10.1007/978-3-031-12748-9_13openalex-snapshot
Towards Real-Time and Energy Efficient Siamese Tracking – A Hardware-Software Approach
inferred← citeshttps://doi.org/10.1007/978-3-031-12748-9_4openalex-snapshot
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-19775-8_3openalex-snapshot
You Already Have It: A Generator-Free Low-Precision DNN Training Framework Using Stochastic Rounding
inferred← citeshttps://doi.org/10.1007/978-3-031-19983-7_12openalex-snapshot
Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features
inferred← citeshttps://doi.org/10.1007/978-3-031-23618-1_37openalex-snapshot
Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA
inferred← citeshttps://doi.org/10.1007/978-3-031-28451-9_12openalex-snapshot
Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification
inferred← citeshttps://doi.org/10.1007/978-3-031-29104-3_4openalex-snapshot
Enabling Neural Network Edge Computing on a Small Robot Vehicle
inferred← citeshttps://doi.org/10.1007/978-3-031-29970-4_8openalex-snapshot
Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification
inferred← citeshttps://doi.org/10.1007/978-3-031-42921-7_19openalex-snapshot
More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding
inferred← citeshttps://doi.org/10.1007/978-3-031-42921-7_27openalex-snapshot
A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing
inferred← citeshttps://doi.org/10.1007/978-3-031-43085-5_31openalex-snapshot
STANN – Synthesis Templates for Artificial Neural Network Inference and Training
inferred← citeshttps://doi.org/10.1007/978-3-031-46077-7_8openalex-snapshot
DAEBI: A Tool for Data Flow and Architecture Explorations of Binary Neural Network Accelerators
inferred← citeshttps://doi.org/10.1007/978-3-031-51500-2_2openalex-snapshot
Modern High-Level Synthesis: Improving Productivity with a Multi-level Approach
inferred← citeshttps://doi.org/10.1007/978-3-031-54277-0_8openalex-snapshot
Embedded Computer Vision for Agricultural Applications
inferred← citeshttps://doi.org/10.1007/978-3-031-55673-9_1openalex-snapshot
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-031-55673-9_7openalex-snapshot
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization
inferred← citeshttps://doi.org/10.1007/978-3-031-63616-5_11openalex-snapshot
Design Optimization for High-Performance Computing Using FPGA
inferred← citeshttps://doi.org/10.1007/978-3-031-78380-7_14openalex-snapshot
I2DS: FPGA-Based Deep Learning Industrial Intrusion Detection System
inferred← citeshttps://doi.org/10.1007/978-3-032-02725-2_14openalex-snapshot
Resource-Efficient Implementation of Convolutional Neural Networks on FPGAs with STANN
inferred← citeshttps://doi.org/10.1007/978-3-032-02725-2_15openalex-snapshot
High-Performance FPGA-Based CNN Acceleration for Real-Time DC Arc Fault Detection
inferred← citeshttps://doi.org/10.1007/978-3-032-06286-4_6openalex-snapshot
TinyML: Applications, Algorithms, Co-design and Implementations
inferred← citeshttps://doi.org/10.1007/978-3-032-29365-7_11openalex-snapshot
Optimizing FPGA-Based Neural Network Ensemble
inferred← citeshttps://doi.org/10.1007/978-3-032-29365-7_16openalex-snapshot
CLAS: A Cross-Layer Approximate Synthesis Framework for LUT-Based DNN Accelerators
inferred← citeshttps://doi.org/10.1007/978-3-032-29365-7_2openalex-snapshot
High Performance Convolutional Neural Network Acceleration on Versal AI Edge Devices for Real Time DC Series Arc Fault Detection
inferred← citeshttps://doi.org/10.1007/978-3-032-29365-7_3openalex-snapshot
LiveFIFO: FPGA-in-the-Loop Buffer Sizing for Dataflow Accelerators
inferred← citeshttps://doi.org/10.1007/978-3-032-30156-7_3openalex-snapshot
Red Grape Detection with Accelerated Artificial Neural Networks in the FPGA’s Programmable Logic
inferred← citeshttps://doi.org/10.1007/978-981-96-7714-6_10openalex-snapshot
Implementations for AI-based Image and Video Coding
inferred← citeshttps://doi.org/10.1007/s00521-022-08034-2openalex-snapshot
An approximate randomization-based neural network with dedicated digital architecture for energy-constrained devices
inferred← citeshttps://doi.org/10.1007/s00521-023-08718-3openalex-snapshot
Deploying deep learning networks based advanced techniques for image processing on FPGA platform
inferred← citeshttps://doi.org/10.1007/s10462-023-10464-wopenalex-snapshot
A comprehensive review of Binary Neural Network
inferred← citeshttps://doi.org/10.1007/s10617-023-09274-8openalex-snapshot
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device
inferred← citeshttps://doi.org/10.1007/s11265-020-01632-0openalex-snapshot
An Efficient FIFO Based Accelerator for Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1007/s11265-021-01733-4openalex-snapshot
Implementation of the PointPillars Network for 3D Object Detection in Reprogrammable Heterogeneous Devices Using FINN
inferred← citeshttps://doi.org/10.1007/s11265-023-01883-7openalex-snapshot
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis
inferred← citeshttps://doi.org/10.1007/s11265-026-01994-xopenalex-snapshot
Low-Cost FPGA-Based Hybrid Defence Against Sticker Attacks for Traffic-Sign Classification
inferred← citeshttps://doi.org/10.1007/s41605-026-00734-wopenalex-snapshot
A knowledge-driven framework for HEP model deployment on heterogeneous hardware
inferred← citeshttps://doi.org/10.1007/s41781-021-00073-zopenalex-snapshot
Charged Particle Tracking via Edge-Classifying Interaction Networks
inferred← citeshttps://doi.org/10.1007/s41781-024-00117-0openalex-snapshot
Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics
inferred← citeshttps://doi.org/10.1007/s42514-020-00059-0openalex-snapshot
A high-throughput scalable BNN accelerator with fully pipelined architecture
inferred← citeshttps://doi.org/10.1016/b978-0-44-329032-9.00016-6openalex-snapshot
Advancing cyber-attack detection for in-vehicle networks: a comparative study of a machine learning-based intrusion detection system
inferred← citeshttps://doi.org/10.1016/b978-0-44-330044-8.00027-0openalex-snapshot
Artificial intelligence
inferred← citeshttps://doi.org/10.1016/j.array.2026.100885openalex-snapshot
A numerical workflow for post-training fixed-point CNN deployment on FPGA
inferred← citeshttps://doi.org/10.1016/j.array.2026.101069openalex-snapshot
The embedded vision preprocessing co-design framework (EVP-CDF): Methodology and decision procedure for real-time detection pipelines
inferred← citeshttps://doi.org/10.1016/j.atech.2026.102580openalex-snapshot
Knowledge distillation and edge deployment of tabular neural models for soil nutrient availability status classification
inferred← citeshttps://doi.org/10.1016/j.bspc.2025.108063openalex-snapshot
HLS-compiled PYNQ-based cardiac arrhythmia detection system leveraging quantized ECG beat images
inferred← citeshttps://doi.org/10.1016/j.future.2026.108823openalex-snapshot
PiC-NDM: A 65nm processing-in-CAM-based binary CNN Accelerator for natural disaster management
inferred← citeshttps://doi.org/10.1016/j.jpdc.2022.04.025openalex-snapshot
Towards a component-based acceleration of convolutional neural networks on FPGAs
inferred← citeshttps://doi.org/10.1016/j.mechrescom.2025.104420openalex-snapshot
FPGA-accelerated Binary Neural Networks as a surrogate model for a viscoplastic constitutive law in impulsively loaded beams
inferred← citeshttps://doi.org/10.1016/j.mejo.2024.106134openalex-snapshot
An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces
inferred← citeshttps://doi.org/10.1016/j.mejo.2025.106556openalex-snapshot
An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse
inferred← citeshttps://doi.org/10.1016/j.micpro.2020.102994openalex-snapshot
Towards resource-frugal deep convolutional neural networks for hyperspectral image segmentation
inferred← citeshttps://doi.org/10.1016/j.micpro.2021.104363openalex-snapshot
A scalable and efficient convolutional neural network accelerator using HLS for a system-on-chip design
inferred← citeshttps://doi.org/10.1016/j.micpro.2025.105225openalex-snapshot
Cardiac arrhythmia classification system: An optimized HLS-based hardware implementation on PYNQ platform
inferred← citeshttps://doi.org/10.1016/j.neucom.2025.129402openalex-snapshot
Deep learning based image classification for embedded devices: A systematic review
inferred← citeshttps://doi.org/10.1016/j.neucom.2025.130417openalex-snapshot
Vision transformers on the edge: A comprehensive survey of model compression and acceleration strategies
inferred← citeshttps://doi.org/10.1016/j.neunet.2025.107256openalex-snapshot
Spiking neural networks on FPGA: A survey of methodologies and recent advancements
inferred← citeshttps://doi.org/10.1016/j.patcog.2020.107281openalex-snapshot
Binary neural networks: A survey
inferred← citeshttps://doi.org/10.1016/j.revip.2024.100091openalex-snapshot
Machine learning for anomaly detection in particle physics
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102156openalex-snapshot
An efficient GPU-accelerated inference engine for binary neural network on mobile phones
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.102257openalex-snapshot
Accelerating DNNs from local to virtualized FPGA in the Cloud: A survey of trends
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103285openalex-snapshot
BIDS: An efficient Intrusion Detection System for in-vehicle networks using a two-stage Binarised Neural Network on low-cost FPGA
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103587openalex-snapshot
Toward TinyDPFL systems for real-time cardiac healthcare: Trends, challenges, and system-level perspectives on AI algorithms, hardware, and edge intelligence
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103842openalex-snapshot
Wavelet-driven Partial Binary Quantization for accelerating deep-learning-based spectrum sensing in embedded systems
inferred← citeshttps://doi.org/10.1038/s42256-021-00356-5openalex-snapshot
Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors
inferred← citeshttps://doi.org/10.1049/cdt2/6214436openalex-snapshot
A Reconfigurable Coarse‐to‐Fine Approach for the Execution of CNN Inference Models in Low‐Power Edge Devices
inferred← citeshttps://doi.org/10.1049/ipr2.12788openalex-snapshot
A lightweight network of near cotton‐coloured impurity detection method in raw cotton based on weighted feature fusion
inferred← citeshttps://doi.org/10.1051/epjconf/202429502032openalex-snapshot
Track reconstruction for the ATLAS Phase-II Event Filter using GNNs on FPGAs
inferred← citeshttps://doi.org/10.1051/epjconf/202533701042openalex-snapshot
Online track reconstruction with graph neural networks on FPGAs for the ATLAS experiment
inferred← citeshttps://doi.org/10.1088/1742-6596/2284/1/012019openalex-snapshot
Operator Optimization Oriented Person Re-Identification
inferred← citeshttps://doi.org/10.1088/1748-0221/21/06/p06039openalex-snapshot
Real-time graph neural networks on FPGAs for the Belle II electromagnetic calorimeter
inferred← citeshttps://doi.org/10.1088/2632-2153/ac0ea1openalex-snapshot
Fast convolutional neural networks on FPGAs with hls4ml
inferred← citeshttps://doi.org/10.1088/2632-2153/ad0d12openalex-snapshot
Exploring machine learning to hardware implementations for large data rate x-ray instrumentation
inferred← citeshttps://doi.org/10.1088/2632-2153/ae9fb5openalex-snapshot
SparsePixels: efficient convolution for sparse data on FPGAs
inferred← citeshttps://doi.org/10.1103/physrevaccelbeams.24.104601openalex-snapshot
Real-time artificial intelligence for accelerator control: A study at the Fermilab Booster
inferred← citeshttps://doi.org/10.1109/access.2019.2933902openalex-snapshot
Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching
inferred← citeshttps://doi.org/10.1109/access.2020.2977454openalex-snapshot
Hyperspectral Band Selection Using Attention-Based Convolutional Neural Networks
inferred← citeshttps://doi.org/10.1109/access.2021.3080136openalex-snapshot
YOLBO: You Only Look Back Once–A Low Latency Object Tracker Based on YOLO and Optical Flow
inferred← citeshttps://doi.org/10.1109/access.2022.3151916openalex-snapshot
A Deep Learning Accelerator Based on a Streaming Architecture for Binary Neural Networks
inferred← citeshttps://doi.org/10.1109/access.2022.3208091openalex-snapshot
A Binarized Neural Network Approach to Accelerate in-Vehicle Network Intrusion Detection
inferred← citeshttps://doi.org/10.1109/access.2023.3234622openalex-snapshot
Most Resource Efficient Matrix Vector Multiplication on FPGAs
inferred← citeshttps://doi.org/10.1109/access.2023.3236974openalex-snapshot
An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration
inferred← citeshttps://doi.org/10.1109/access.2023.3258360openalex-snapshot
A Systematic Literature Review on Binary Neural Networks
inferred← citeshttps://doi.org/10.1109/access.2023.3324877openalex-snapshot
A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding
inferred← citeshttps://doi.org/10.1109/access.2024.3514325openalex-snapshot
Better Scalability: Improvement of Block-Based CNN Accelerator for FPGAs
inferred← citeshttps://doi.org/10.1109/access.2025.3577908openalex-snapshot
FPG-AI RNN: A Technology-Agnostic Framework for the Automatic Acceleration of LSTM/GRU-Based Models on FPGAs
inferred← citeshttps://doi.org/10.1109/aero53065.2022.9843614openalex-snapshot
Accelerated Radiation Test on Quantized Neural Networks trained with Fault Aware Training
inferred← citeshttps://doi.org/10.1109/aiotc71250.2026.11688805openalex-snapshot
Mixed-Precision Quantization Method for FPGA-Based Sparse 4D mmWave Radar Point-Cloud Enhancment
inferred← citeshttps://doi.org/10.1109/apccas47518.2019.8953134openalex-snapshot
Using Neuroevolved Binary Neural Networks to solve reinforcement learning environments
inferred← citeshttps://doi.org/10.1109/apccas62602.2024.10808367openalex-snapshot
Lightweight Binary Neural Networks for Edge Devices
inferred← citeshttps://doi.org/10.1109/asap54787.2022.00025openalex-snapshot
Full-BNN: A Low Storage and Power Consumption Time-Domain Architecture based on FPGA
inferred← citeshttps://doi.org/10.1109/asicon66040.2025.11326039openalex-snapshot
A Low-Cost Multiplier-Free Accelerator for Binary Neural Network
inferred← citeshttps://doi.org/10.1109/asyu58738.2023.10296630openalex-snapshot
Implementation and Optimization of LeNet-5 Model for Handwritten Digits Recognition on FPGAs using Brevitas and FINN
inferred← citeshttps://doi.org/10.1109/biocas54905.2022.9948601openalex-snapshot
Flexible design methodology for spike encoding implementation on FPGA
inferred← citeshttps://doi.org/10.1109/bip60195.2023.10379257openalex-snapshot
Acceleration of Fully Connected Layers on FPGA using the Strassen Matrix Multiplication
inferred← citeshttps://doi.org/10.1109/candar51075.2020.00039openalex-snapshot
An implementation methodology for Neural Network on a Low-end FPGA Board
inferred← citeshttps://doi.org/10.1109/ciss64860.2025.10944746openalex-snapshot
Resource and Performance Improvements of Optimized Convolutional Neural Networks for FPGA Implementations of Automatic Modulation Recognition
inferred← citeshttps://doi.org/10.1109/cloudnet53349.2021.9657109openalex-snapshot
The Open Cloud Testbed (OCT): A Platform for Research into new Cloud Technologies
inferred← citeshttps://doi.org/10.1109/coins61597.2024.10622147openalex-snapshot
A User-Friendly Ecosystem for AI FPGA-Based Accelerators
inferred← citeshttps://doi.org/10.1109/comst.2026.3682638openalex-snapshot
Model Compression for Sustainable AI in xG Wireless Networks: Recent Advances, Challenges, and Future Directions
inferred← citeshttps://doi.org/10.1109/concapan63470.2024.10933896openalex-snapshot
LLM Acceleration on FPGAs: A Comparative Study of Layer and Spatial Accelerators
inferred← citeshttps://doi.org/10.1109/coolchips52128.2021.9410327openalex-snapshot
LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586110openalex-snapshot
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
inferred← citeshttps://doi.org/10.1109/dcis58620.2023.10335989openalex-snapshot
Implementing a CNN in FPGA Programmable Logic for NILM Application
inferred← citeshttps://doi.org/10.1109/ddecs57882.2023.10139758openalex-snapshot
A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel
inferred← citeshttps://doi.org/10.1109/dft52944.2021.9568280openalex-snapshot
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00025openalex-snapshot
Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00032openalex-snapshot
DSL-Based SNN Accelerator Design Using Chisel
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00034openalex-snapshot
Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00046openalex-snapshot
Partial Reconfiguration for Energy-Efficient Inference on FPGA: A Case Study with ResNet-18
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00062openalex-snapshot
Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00073openalex-snapshot
High Throughput and Low Bandwidth Demand: Accelerating CNN Inference Block-by-block on FPGAs
inferred← citeshttps://doi.org/10.1109/dsd67783.2025.00080openalex-snapshot
Hardware-Aware Feature Extraction Quantisation for Real-Time Visual Odometry on FPGA Platforms
inferred← citeshttps://doi.org/10.1109/dspa64310.2025.10977895openalex-snapshot
Boosting DNN Efficiency: Replacing FC Layers with Graph Embeddings for Hardware Acceleration
inferred← citeshttps://doi.org/10.1109/dttis62212.2024.10780417openalex-snapshot
IJTAG-compatible Symptom-based SEU Monitors for FPGA DNN Accelerators
inferred← citeshttps://doi.org/10.1109/edge60047.2023.00019openalex-snapshot
DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs
inferred← citeshttps://doi.org/10.1109/eicars71536.2026.11694934openalex-snapshot
An FPGA-Based Unified Processing Element for INT8/Binary Quantization and its Scalable Array Design
inferred← citeshttps://doi.org/10.1109/fccm48280.2020.00010openalex-snapshot
High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00010openalex-snapshot
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00014openalex-snapshot
HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00027openalex-snapshot
unzipFPGA: Enhancing FPGA-based CNN Engines with On-the-Fly Weights Generation
inferred← citeshttps://doi.org/10.1109/fccm51124.2021.00061openalex-snapshot
TwinDNN: A Tale of Two Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786107openalex-snapshot
Reverse Engineering Neural Network Folding with Remote FPGA Power Analysis
inferred← citeshttps://doi.org/10.1109/fccm62733.2025.00062openalex-snapshot
NoH: NoC Compilation in High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/fpl.2019.00064openalex-snapshot
TensorFlow to Cloud FPGAs: Tradeoffs for Accelerating Deep Neural Networks
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00015openalex-snapshot
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00061openalex-snapshot
Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00062openalex-snapshot
Feature dimensionality in CNN acceleration for high-throughput network intrusion detection
inferred← citeshttps://doi.org/10.1109/fpl57034.2022.00069openalex-snapshot
SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00049openalex-snapshot
PASS: Exploiting Post-Activation Sparsity in Streaming Architectures for CNN Acceleration
inferred← citeshttps://doi.org/10.1109/fpl60245.2023.00066openalex-snapshot
Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML
inferred← citeshttps://doi.org/10.1109/fpl64840.2024.00048openalex-snapshot
Shedding the Bits: Pushing the Boundaries of Quantization with Minifloats on FPGAs
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00018openalex-snapshot
FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00026openalex-snapshot
F 2 Opt: Novel Fine-Tuning and Folding Algorithms for FPGA-Based DNN Accelerators
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00048openalex-snapshot
Hybrid Weightless Neural Networks for Efficient Edge Inference
inferred← citeshttps://doi.org/10.1109/fpl68686.2025.00062openalex-snapshot
Analytical Buffer Sizing for Neural Network Inference Applications on FPGAs
inferred← citeshttps://doi.org/10.1109/hora58378.2023.10155783openalex-snapshot
Real-Time Hardware Acceleration of Low Precision Quantized Custom Neural Network Model on ZYNQ SoC
inferred← citeshttps://doi.org/10.1109/host68814.2026.11604627openalex-snapshot
Talking Traces: Audio Reconstruction Power Side-Channel Attack on Neural Network FPGA Accelerators
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071076openalex-snapshot
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices
inferred← citeshttps://doi.org/10.1109/hpcs48598.2019.9188213openalex-snapshot
Performance-Oriented Neural Architecture Search
inferred← citeshttps://doi.org/10.1109/hpec43674.2020.9286194openalex-snapshot
CQNN: a CGRA-based QNN Framework
inferred← citeshttps://doi.org/10.1109/hpec49654.2021.9622877openalex-snapshot
A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs
inferred← citeshttps://doi.org/10.1109/hpec58863.2023.10363454openalex-snapshot
Machine Learning Across Network-Connected FPGAs
inferred← citeshttps://doi.org/10.1109/iccad51958.2021.9643474openalex-snapshot
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240860openalex-snapshot
FPGA-CC: Confidential Containers for Virtualized FPGAs
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00079openalex-snapshot
Accelerating Hybrid Quantized Neural Networks on Multi-tenant Cloud FPGA
inferred← citeshttps://doi.org/10.1109/iccd56317.2022.00081openalex-snapshot
VEA: An FPGA-Based Voxel Encoding Accelerator for 3D Object Detection with LiDAR
inferred← citeshttps://doi.org/10.1109/iccv51070.2023.00560openalex-snapshot
MST-compression: Compressing and Accelerating Binary Neural Networks with Minimum Spanning Tree
inferred← citeshttps://doi.org/10.1109/iccv51070.2023.01558openalex-snapshot
A2Q: Accumulator-Aware Quantization with Guaranteed Overflow Avoidance
inferred← citeshttps://doi.org/10.1109/icecs58634.2023.10382715openalex-snapshot
Pipelined Architecture for a Semantic Segmentation Neural Network on FPGA
inferred← citeshttps://doi.org/10.1109/icee67165.2025.11409756openalex-snapshot
Efficient Encrypted Memory for Edge AI Using Co-Design
inferred← citeshttps://doi.org/10.1109/icfpt47387.2019.00076openalex-snapshot
Evolved Binary Neural Networks Through Harnessing FPGA Capabilities
inferred← citeshttps://doi.org/10.1109/icfpt51103.2020.00016openalex-snapshot
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA
inferred← citeshttps://doi.org/10.1109/icfpt52863.2021.9609813openalex-snapshot
StreamSVD: Low-rank Approximation and Streaming Accelerator Co-design
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00024openalex-snapshot
LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA
inferred← citeshttps://doi.org/10.1109/icfpt59805.2023.00025openalex-snapshot
SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices
inferred← citeshttps://doi.org/10.1109/icfpt64416.2024.11113391openalex-snapshot
FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00013openalex-snapshot
LL-ViT: Edge Deployable Vision Transformers with Look Up Table Neurons
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00032openalex-snapshot
Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00033openalex-snapshot
Power-Efficient FPGA Acceleration of Quantised Neural Networks Through Safe Undervolting
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00040openalex-snapshot
LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-Learning Accelerators
inferred← citeshttps://doi.org/10.1109/icfpt67023.2025.00044openalex-snapshot
Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators
inferred← citeshttps://doi.org/10.1109/icip46576.2022.9897752openalex-snapshot
Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization
inferred← citeshttps://doi.org/10.1109/icit58233.2024.10540960openalex-snapshot
An FPGA-Based Intrusion Detection System Using Binarised Neural Network for CAN Bus Systems
inferred← citeshttps://doi.org/10.1109/icm66518.2025.11321327openalex-snapshot
A Streaming SNN Accelerator Exploiting Temporal-Spatial Sparsity for Automatic Modulation Classification
inferred← citeshttps://doi.org/10.1109/icm66518.2025.11322468openalex-snapshot
Fast and Resource-Aware Implementation of Recurrent Neural Network Accelerators on FPGAs
inferred← citeshttps://doi.org/10.1109/icm66518.2025.11322507openalex-snapshot
TinyCNet: Turning Pretrained-CNNs to Edge-Ready FPGA Logic
inferred← citeshttps://doi.org/10.1109/icmlas67792.2026.11483684openalex-snapshot
GAN-QNN: A Resource-Efficient FPGA-Based IDS for Unknown Attacks in CAN Networks
inferred← citeshttps://doi.org/10.1109/icmlcn64995.2025.11140290openalex-snapshot
FPGA-Powered Environment Awareness via Quantized Neural Networks for LiDAR-Aided mm-Wave Beam Prediction
inferred← citeshttps://doi.org/10.1109/icrc2020.2020.00018openalex-snapshot
Training Deep Neural Networks with Constrained Learning Parameters
inferred← citeshttps://doi.org/10.1109/icsmacs68968.2026.11628492openalex-snapshot
Chaos-based Secure and Parametric Datasets-Aware Multi-Layer Perceptron Acceleration on FPGA
inferred← citeshttps://doi.org/10.1109/icssit69151.2026.11656582openalex-snapshot
Design & FPGA Implementation of 32-Bit Risc-V Processor with MAC & Perceptron Accelerators
inferred← citeshttps://doi.org/10.1109/icufn61752.2024.10625618openalex-snapshot
Fast prototyping of Quantized neural networks on an FPGA edge computing device with Brevitas and FINN
inferred← citeshttps://doi.org/10.1109/ihmsc62065.2024.00018openalex-snapshot
Customized BNN architectures for Compressed Sensing and FPGA implementations
inferred← citeshttps://doi.org/10.1109/ijcnn54540.2023.10191784openalex-snapshot
Quantization Modes for Neural Network Inference: ASIC Implementation Trade-offs
inferred← citeshttps://doi.org/10.1109/ijcnn55064.2022.9892671openalex-snapshot
Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks
inferred← citeshttps://doi.org/10.1109/indin45523.2021.9557519openalex-snapshot
Platform Generation for Edge AI Devices with Custom Hardware Accelerators
inferred← citeshttps://doi.org/10.1109/infocom52122.2024.10621400openalex-snapshot
Efficient and Effective In-Vehicle Intrusion Detection System using Binarized Convolutional Neural Network
inferred← citeshttps://doi.org/10.1109/infocomwkshps54753.2022.9798375openalex-snapshot
Network Attached FPGAs in the Open Cloud Testbed (OCT)
inferred← citeshttps://doi.org/10.1109/inista55318.2022.9894261openalex-snapshot
Performance Evaluation of Low-Precision Quantized LeNet and ConvNet Neural Networks
inferred← citeshttps://doi.org/10.1109/iolts60994.2024.10616081openalex-snapshot
VANDOR: Mitigating SEUs into Quantized Neural Networks
inferred← citeshttps://doi.org/10.1109/ipdpsw59300.2023.00026openalex-snapshot
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs
inferred← citeshttps://doi.org/10.1109/iraset68627.2026.11538436openalex-snapshot
Neural Network Quantization for FPGA: A Unified Taxonomy and Survey of Methods, Platforms, and Deployment
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9180867openalex-snapshot
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator
inferred← citeshttps://doi.org/10.1109/iscas45731.2020.9181037openalex-snapshot
VersaTile Convolutional Neural Network Mapping on FPGAs
inferred← citeshttps://doi.org/10.1109/iscas51556.2021.9401780openalex-snapshot
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043488openalex-snapshot
Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11044227openalex-snapshot
Bit-Width-Aware Design Environment for Few-Shot Learning on Edge AI Hardware
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558120openalex-snapshot
DNNMapper: An Elastic Framework for Mapping DNNs to Multi-die FPGAs
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10558457openalex-snapshot
ACNNE: An Adaptive Convolution Engine for CNNs Acceleration Exploiting Partial Reconfiguration on FPGAs
inferred← citeshttps://doi.org/10.1109/ismvl52857.2022.00030openalex-snapshot
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks
inferred← citeshttps://doi.org/10.1109/ispa63168.2024.00143openalex-snapshot
Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML
inferred← citeshttps://doi.org/10.1109/ispass64960.2025.00030openalex-snapshot
An Analytical Cost Model for Fast Evaluation of Multiple Compute-Engine CNN Accelerators
inferred← citeshttps://doi.org/10.1109/ispdc55340.2022.00014openalex-snapshot
Coarse-Grained Floorplanning for streaming CNN applications on Multi-Die FPGAs
showing the first 200 of 440 · page through all 440
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.