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A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.compeleceng.2013.06.005openalex-snapshot
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
inferredcites →https://doi.org/10.1016/j.sysarc.2007.01.013openalex-snapshot
Automated memory-aware application distribution for Multi-processor System-on-Chips
inferredcites →https://doi.org/10.1023/a:1008899229802openalex-snapshot
System-Level Synthesis Using Evolutionary Algorithms
inferredcites →https://doi.org/10.1109/date.2010.5457211openalex-snapshot
An industrial design space exploration framework for supporting run-time resource management on multi-core systems
inferredcites →https://doi.org/10.1109/date.2011.5763071openalex-snapshot
Achieving composability in NoC-based MPSoCs through QoS management at software level
inferredcites →https://doi.org/10.1109/estimedia.2012.6507026openalex-snapshot
Multi-objective mapping optimization via problem decomposition for many-core systems
inferredcites →https://doi.org/10.1109/ipdps.2004.1303088openalex-snapshot
Worst case execution time prediction by static program analysis
inferredcites →https://doi.org/10.1109/isorcw.2015.48openalex-snapshot
Design Methodology and Run-Time Management for Predictable Many-Core Systems
inferredcites →https://doi.org/10.1109/issoc.2005.1595650openalex-snapshot
Energy Model of Networks-on-Chip and a Bus
inferredcites →https://doi.org/10.1109/issoc.2006.321966openalex-snapshot
Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management
inferredcites →https://doi.org/10.1109/mdt.2005.99openalex-snapshot
Æthereal Network on Chip:Concepts, Architectures, and Implementations
inferredcites →https://doi.org/10.1109/rsp.2007.26openalex-snapshot
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1109/tcad.2008.2003301openalex-snapshot
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
inferredcites →https://doi.org/10.1145/1119772.1119818openalex-snapshot
Energy-aware mapping for tile-based NoC architectures under performance constraints
inferredcites →https://doi.org/10.1145/1347375.1347389openalex-snapshot
The worst-case execution-time problem—overview of methods and survey of tools
inferredcites →https://doi.org/10.1145/1403375.1403427openalex-snapshot
Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSoC)
inferredcites →https://doi.org/10.1145/1403375.1403709openalex-snapshot
Dynamic task allocation strategies in MPSoC for soft real-time applications
inferredcites →https://doi.org/10.1145/1629911.1630147openalex-snapshot
A parameterized compositional multi-dimensional multiple-choice knapsack heuristic for CMP run-time management
inferredcites →https://doi.org/10.1145/1999946.1999979openalex-snapshot
Dynamic decentralized mapping of tree-structured applications on NoC architectures
inferredcites →https://doi.org/10.1145/2039370.2039393openalex-snapshot
Symbolic design space exploration for multi-mode reconfigurable systems
inferredcites →https://doi.org/10.1145/2228360.2228480openalex-snapshot
Executing synchronous dataflow graphs on a SPM-based multicore architecture
inferredcites →https://doi.org/10.1145/2390191.2390200openalex-snapshot
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
inferredcites →https://doi.org/10.1145/2463209.2488734openalex-snapshot
Mapping on multi/many-core systems
inferredcites →https://doi.org/10.1145/2463209.2488857openalex-snapshot
Reliable on-chip systems in the nano-era
inferredcites →https://doi.org/10.1145/2541012.2541014openalex-snapshot
A fast and scalable multidimensional multiple-choice knapsack heuristic
inferredcites →https://doi.org/10.1145/2584658openalex-snapshot
Dynamic Behavior Specification and Dynamic Mapping for Real-Time Embedded Systems
inferredcites →https://doi.org/10.1145/2656075.2656102openalex-snapshot
Towards scalable symbolic routing for multi-objective networked embedded system design and optimization
inferredcites →https://doi.org/10.1145/2680542openalex-snapshot
A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1145/2744769.2744840openalex-snapshot
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures
inferredcites →https://doi.org/10.1145/2906363.2906370openalex-snapshot
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs
inferredcites →https://doi.org/10.1145/3139258.3139278openalex-snapshot
Predictable run-time mapping reconfiguration for real-time applications on many-core systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cpe.5149openalex-snapshot
*‐Predictable MPSoC execution of real‐time control applications using invasive computing
inferred← citeshttps://doi.org/10.1007/978-3-030-18656-2_4openalex-snapshot
Resource-Aware Parameter Tuning for Real-Time Applications
inferred← citeshttps://doi.org/10.1007/s10617-023-09271-xopenalex-snapshot
Predictable timing behavior of gracefully degrading automotive systems
inferred← citeshttps://doi.org/10.1038/s41598-026-65003-8openalex-snapshot
Advanced quantum computing-driven digital twin for energy and timing optimization in low-power VLSI circuits &IoT devices
inferred← citeshttps://doi.org/10.1109/dsd53832.2021.00066openalex-snapshot
Checkpointing Period Optimization of Distributed Fail-Operational Automotive Applications
inferred← citeshttps://doi.org/10.1109/nocarc57472.2022.9911366openalex-snapshot
Scalable Run-time Task Mapping on BNoC Topology Focusing on Energy-efficiency
inferred← citeshttps://doi.org/10.1109/rtss46320.2019.00029openalex-snapshot
Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems
inferred← citeshttps://doi.org/10.1109/tnano.2023.3237128openalex-snapshot
The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution
inferred← citeshttps://doi.org/10.1145/3529230openalex-snapshot
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs
inferred← citeshttps://doi.org/10.23919/date51398.2021.9473950openalex-snapshot
Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive Applications
inferred← citeshttps://doi.org/10.3390/jlpea10040038openalex-snapshot
Hybrid Application Mapping for Composable Many-Core Systems: Overview and Future Perspective
inferred← citeshttps://doi.org/10.3390/jlpea11010007openalex-snapshot
Reliability-Aware Resource Management in Multi-/Many-Core Systems: A Perspective Paper
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