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InvisiSpec

https://doi.org/10.1145/3352460.3361129
0 signed · 25 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/micro.2018.00042openalex-snapshot
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.2139/ssrn.4511910openalex-extracted
inferred← citeshttps://doi.org/10.5281/zenodo.14889037zenodo-depositor-declared
inferred← citeshttps://doi.org/10.1007/978-3-030-80825-9_8openalex-snapshot
Specularizer : Detecting Speculative Execution Attacks via Performance Tracing
inferred← citeshttps://doi.org/10.1007/978-3-031-46479-9_1openalex-snapshot
Cybersecurity Landscape for Computer Systems
inferred← citeshttps://doi.org/10.1007/978-3-031-46479-9_4openalex-snapshot
Spectre and Meltdown Detection Using Explainable AI
inferred← citeshttps://doi.org/10.1007/978-3-031-50521-8_14openalex-snapshot
Automatic and Incremental Repair for Speculative Information Leaks
inferred← citeshttps://doi.org/10.1007/978-3-662-64322-8_14openalex-snapshot
Specfuscator: Evaluating Branch Removal as a Spectre Mitigation
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_10-1openalex-snapshot
Secure Processor Architectures
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_10openalex-snapshot
Secure Processor Architectures
inferred← citeshttps://doi.org/10.1007/s13389-022-00289-8openalex-snapshot
A framework for leaking secrets to past instructions
inferred← citeshttps://doi.org/10.1016/j.is.2020.101524openalex-snapshot
Winter is here! A decade of cache-based side-channel attacks, detection & mitigation for RSA
inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103107openalex-snapshot
SecurityCloak: Protection against cache timing and speculative memory access attacks
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00050openalex-snapshot
Enhancing and Exploiting Contiguity for Fast Memory Virtualization
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom59178.2023.00089openalex-snapshot
DPFCFI: A Hardware-Based Forward Control-Flow Integrity for Architecture and Microarchitecture
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528744openalex-snapshot
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments
inferred← citeshttps://doi.org/10.1109/svcc56964.2023.10165527openalex-snapshot
Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks
inferred← citeshttps://doi.org/10.1145/3297858.3304060openalex-snapshot
Context-Sensitive Fencing
inferred← citeshttps://doi.org/10.1145/3491218openalex-snapshot
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling
inferred← citeshttps://doi.org/10.1145/3634737.3637651openalex-snapshot
Beyond Over-Protection: A Targeted Approach to Spectre Mitigation and Performance Optimization
inferred← citeshttps://doi.org/10.1145/3658644.3690201openalex-snapshot
Eclipse: Preventing Speculative Memory-error Abuse with Artificial Data Dependencies
inferred← citeshttps://doi.org/10.12794/metadc2332527openalex-snapshot
A Study of Mitigation Methods for Speculative Cache Side Channel Attacks
inferred← citeshttps://doi.org/10.23919/date58400.2024.10546575openalex-snapshot
Three Sidekicks to Support Spectre Countermeasures
inferred← citeshttps://doi.org/10.5281/zenodo.14783060openalex-snapshot
AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
inferred← citeshttps://doi.org/10.70675/c72ce299z22adz4e68z90aaz9b80ab756d99openalex-snapshot
Modeling of micro-architecture for security with gem5
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