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Meltdown
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11605805_1openalex-snapshot
Cache Attacks and Countermeasures: The Case of AES
inferredcites →https://doi.org/10.1007/978-3-030-29959-0_14openalex-snapshot
NetSpectre: Read Arbitrary Memory over Network
inferredcites →https://doi.org/10.1007/978-3-319-40667-1_14openalex-snapshot
Flush+Flush: A Fast and Stealthy Cache Attack
inferredcites →https://doi.org/10.1007/978-3-319-62105-0_11openalex-snapshot
KASLR is Dead: Long Live KASLR
inferredcites →https://doi.org/10.1007/s13389-016-0141-6openalex-snapshot
A survey of microarchitectural timing attacks and countermeasures on contemporary hardware
inferredcites →https://doi.org/10.1016/0026-2692(93)90111-qopenalex-snapshot
Computer architecture: a quantitative approach
inferredcites →https://doi.org/10.1109/hotchips.2016.7936205openalex-snapshot
Samsung exynos M1 processor
inferredcites →https://doi.org/10.1109/sp.2013.23openalex-snapshot
Practical Timing Side Channel Attacks against Kernel Space ASLR
inferredcites →https://doi.org/10.1109/sp.2019.00002openalex-snapshot
Spectre Attacks: Exploiting Speculative Execution
inferredcites →https://doi.org/10.1109/sp.2019.00087openalex-snapshot
RIDL: Rogue In-Flight Data Load
inferredcites →https://doi.org/10.1145/2660267.2660356openalex-snapshot
Cross-Tenant Side-Channel Attacks in PaaS Clouds
inferredcites →https://doi.org/10.1145/2976749.2978321openalex-snapshot
Breaking Kernel Address Space Layout Randomization with Intel TSX
inferredcites →https://doi.org/10.2200/s00346ed1v01y201104cac016openalex-snapshot
A Primer on Memory Consistency and Cache Coherence
inferredcites →https://doi.org/10.48550/arxiv.1807.03757openalex-snapshot
Speculative Buffer Overflows: Attacks and Defenses
inferredcites →https://doi.org/10.48550/arxiv.1903.01843openalex-snapshot
SMoTherSpectre: exploiting speculative execution through port contention
inferredcites →https://doi.org/10.48550/arxiv.1905.05726openalex-snapshot
ZombieLoad: Cross-Privilege-Boundary Data Sampling
inferredcites →https://doi.org/10.5281/zenodo.375513openalex-snapshot
Prefetch Side-Channel Attacks: Bypassing Smap And Kernel Aslr
inferredcites →https://doi.org/10.5281/zenodo.55454openalex-snapshot
Cache Template Attacks: Automating Attacks On Inclusive Last-Level Caches
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/nem.2288openalex-snapshot
Domain‐Adaptive Power Profiling Analysis Strategy for the Metaverse
inferred← citeshttps://doi.org/10.1002/widm.70034openalex-snapshot
Hardware Security in the Connected World
inferred← citeshttps://doi.org/10.1007/978-3-030-65277-7_21openalex-snapshot
Adaptively Secure Threshold Symmetric-Key Encryption
inferred← citeshttps://doi.org/10.1007/978-3-030-90513-2_10openalex-snapshot
IT Security Measures and Their Relation to Data Protection
inferred← citeshttps://doi.org/10.1007/978-3-031-13185-1_20openalex-snapshot
Explaining Hyperproperty Violations
inferred← citeshttps://doi.org/10.1007/978-3-031-15839-1_4openalex-snapshot
Bounded Delay Timed Channel Coding
inferred← citeshttps://doi.org/10.1007/978-3-031-38554-4_24openalex-snapshot
Revisiting Security Estimation for LWE with Hints from a Geometric Perspective
inferred← citeshttps://doi.org/10.1007/978-3-031-46479-9_4openalex-snapshot
Spectre and Meltdown Detection Using Explainable AI
inferred← citeshttps://doi.org/10.1007/978-3-031-74776-2_11openalex-snapshot
Quantitative Static Timing Analysis
inferred← citeshttps://doi.org/10.1007/978-3-031-80408-3_13openalex-snapshot
“There’s Always Another Counter”: Detecting Micro-Architectural Attacks in a Probabilistically Interleaved Malicious/Benign Setting
inferred← citeshttps://doi.org/10.1007/978-3-031-93254-0_8openalex-snapshot
S-TSG: Description Model of Transient Execution Attacks in Intel SGX
inferred← citeshttps://doi.org/10.1007/978-3-032-00627-1_6openalex-snapshot
Fast and Efficient Secure L1 Caches for SMT
inferred← citeshttps://doi.org/10.1007/978-3-032-07894-0_5openalex-snapshot
Identifying Potential Timing Leakages from Hardware Design with Precondition Synthesis
inferred← citeshttps://doi.org/10.1007/978-94-6265-635-2_2openalex-snapshot
The Technological and Societal Landscape
inferred← citeshttps://doi.org/10.1007/978-981-16-4486-3_3openalex-snapshot
A Systematic Review of Challenges and Techniques of Privacy-Preserving Machine Learning
inferred← citeshttps://doi.org/10.1007/978-981-19-7636-0_4openalex-snapshot
Current Application Fields
inferred← citeshttps://doi.org/10.1007/978-981-96-2794-3_52openalex-snapshot
Side-Channel Attack Based on Artificial Intelligence
inferred← citeshttps://doi.org/10.1007/978-981-96-5032-3_8openalex-snapshot
Evaluating Kernel Anti-Exploitation Capabilities: A Scalable and General Framework Based on Evaluatology
inferred← citeshttps://doi.org/10.1007/s10586-026-06130-9openalex-snapshot
Enhancing spectre attack detection with conditional GAN data augmentation and LSTM classification
inferred← citeshttps://doi.org/10.1007/s11390-021-1249-4openalex-snapshot
Secure Speculation via Speculative Secret Flow Tracking
inferred← citeshttps://doi.org/10.1007/s13389-023-00344-yopenalex-snapshot
Breaking KASLR on mobile devices without any use of cache memory (extended version)
inferred← citeshttps://doi.org/10.1007/s41635-026-00180-6openalex-snapshot
AISELF: An LLM-based Automated Interleaved Speculative-Execution Leakage Detection Framework
inferred← citeshttps://doi.org/10.1016/j.compeleceng.2025.110089openalex-snapshot
zk-DASTARK: A quantum-resistant, data authentication and zero-knowledge proof scheme for protecting data feed to smart contracts
inferred← citeshttps://doi.org/10.1016/j.cose.2023.103255openalex-snapshot
Extending the classical side-channel analysis framework to access-driven cache attacks
inferred← citeshttps://doi.org/10.1016/j.cose.2024.104072openalex-snapshot
Hardware information flow tracking based on lightweight path awareness
inferred← citeshttps://doi.org/10.1016/j.cose.2024.104297openalex-snapshot
A combined side-channel and transient execution attack scheme on RISC-V processors
inferred← citeshttps://doi.org/10.1016/j.cose.2025.104810openalex-snapshot
Memory under siege: A comprehensive survey of side-Channel attacks on memory
inferred← citeshttps://doi.org/10.1016/j.cose.2025.104817openalex-snapshot
Attacks, defenses and perspectives for the runtime security of RISC-V IoT devices: A review
inferred← citeshttps://doi.org/10.1016/j.cose.2026.105174openalex-snapshot
Hardware-assisted isolation of Rust from unsafe languages on ARM
inferred← citeshttps://doi.org/10.1016/j.fmre.2025.08.017openalex-snapshot
TRUST: A toolkit for TEE-assisted secure outsourced computation over integers
inferred← citeshttps://doi.org/10.1016/j.is.2021.101769openalex-snapshot
Detecting inorganic financial campaigns on Twitter
inferred← citeshttps://doi.org/10.1016/j.jpdc.2023.104733openalex-snapshot
HyperTP: A unified approach for live hypervisor replacement in datacenters
inferred← citeshttps://doi.org/10.1016/j.mejo.2026.107322openalex-snapshot
SAVP: Self-validating secure speculation via address-based value prediction
inferred← citeshttps://doi.org/10.1016/j.micpro.2024.105121openalex-snapshot
Lower the RISC: Designing optical-probing-attack-resistant cores
inferred← citeshttps://doi.org/10.1016/j.micpro.2026.105288openalex-snapshot
The remarkable evolution of microelectronics and microprocessors: Devices that changed the world
inferred← citeshttps://doi.org/10.1016/j.sysarc.2023.102997openalex-snapshot
One more set: Mitigating conflict-based cache side-channel attacks by extending cache set
inferred← citeshttps://doi.org/10.1038/s41928-024-01312-yopenalex-snapshot
Safe, secure and trustworthy compute-in-memory accelerators
inferred← citeshttps://doi.org/10.1049/cmu2.12759openalex-snapshot
Survey of research on confidential computing
inferred← citeshttps://doi.org/10.1080/01611194.2024.2328548openalex-snapshot
Fault-assisted side-channel analysis of HMAC-Streebog
inferred← citeshttps://doi.org/10.1103/physrevapplied.21.040501openalex-snapshot
Post-quantum cryptography and the quantum future of cybersecurity
inferred← citeshttps://doi.org/10.1108/ebr-11-2019-0297openalex-snapshot
Blockchain in general management and economics: a systematic literature review
inferred← citeshttps://doi.org/10.1109/access.2020.3024243openalex-snapshot
Reverse Engineering of Intel Microcode Update Structure
inferred← citeshttps://doi.org/10.1109/access.2022.3195508openalex-snapshot
A Refinement-Based Approach to Spectre Invulnerability Verification
inferred← citeshttps://doi.org/10.1109/access.2022.3216325openalex-snapshot
GhostLeg: Selective Memory Coalescing for Secure GPU Architecture
inferred← citeshttps://doi.org/10.1109/access.2023.3337043openalex-snapshot
Hardware-Based Software Control Flow Integrity: Review on the State-of-the-Art Implementation Technology
inferred← citeshttps://doi.org/10.1109/access.2025.3609234openalex-snapshot
Interrupt Caching: A Hardware-Assisted Interrupt Handling to Enhance System Responsiveness
inferred← citeshttps://doi.org/10.1109/acdsa65407.2025.11165916openalex-snapshot
"vcd2df" - Leveraging Data Science Insights for Hardware Security Research
inferred← citeshttps://doi.org/10.1109/acsac63791.2024.00052openalex-snapshot
I’ll Be There for You! Perpetual Availability in the A8 MVX System
inferred← citeshttps://doi.org/10.1109/acsac63791.2024.00056openalex-snapshot
SECvma: Virtualization-based Linux Kernel Protection for Arm
inferred← citeshttps://doi.org/10.1109/acsac67867.2025.00028openalex-snapshot
MimicCall: Bypassing System Call Filters via Kernel Function Redundancy
inferred← citeshttps://doi.org/10.1109/acsacw65225.2024.00033openalex-snapshot
Formal Trust and Threat Modeling Using Large Language Models
inferred← citeshttps://doi.org/10.1109/aimla67915.2026.11522419openalex-snapshot
Cross-Layer Detection of Stealthy Side-Channel Attacks in Multi-Tenant Clouds with Statistical False-Positive Control
inferred← citeshttps://doi.org/10.1109/ase51524.2021.9678636openalex-snapshot
CorbFuzz: Checking Browser Security Policies with Fuzzing
inferred← citeshttps://doi.org/10.1109/asp-dac66049.2026.11420553openalex-snapshot
RTL Verification for Secure Speculation Using Cascaded Two-Phase Information Flow Tracking
inferred← citeshttps://doi.org/10.1109/ats59501.2023.10317944openalex-snapshot
Security Verification of RISC-V System Based on ISA Level Information Flow Tracking
inferred← citeshttps://doi.org/10.1109/bigdata50022.2020.9378018openalex-snapshot
Machine Learning Methods for Anomaly Detection in Industrial Control Systems
inferred← citeshttps://doi.org/10.1109/cases60062.2024.00007openalex-snapshot
Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions
inferred← citeshttps://doi.org/10.1109/ccgrid54584.2022.00036openalex-snapshot
SGX-Bundler: speeding up enclave transitions for IO-intensive applications
inferred← citeshttps://doi.org/10.1109/ccgrid68966.2026.00076openalex-snapshot
Kumo: A Security-Focused Serverless Cloud Simulator
inferred← citeshttps://doi.org/10.1109/cisce65916.2025.11065647openalex-snapshot
HSBP: A Hybrid Secure Branch Predictor Design Against Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/cloud60044.2023.00040openalex-snapshot
Making Your Program Oblivious: A Comparative Study for Side-channel-Safe Confidential Computing
inferred← citeshttps://doi.org/10.1109/cluster59578.2024.00046openalex-snapshot
A High-Performance and Fast-Recovery Scheme for Secure Non-Volatile Memory Systems
inferred← citeshttps://doi.org/10.1109/coins57856.2023.10189332openalex-snapshot
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core
inferred← citeshttps://doi.org/10.1109/dac18072.2020.9218725openalex-snapshot
Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247721openalex-snapshot
Lightning Talk: The Incredible Shrinking Black Box Model
inferred← citeshttps://doi.org/10.1109/dac63849.2025.11132905openalex-snapshot
FastPath: A Hybrid Approach for Efficient Hardware Security Verification
inferred← citeshttps://doi.org/10.1109/ddecs63720.2025.11006772openalex-snapshot
S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors
inferred← citeshttps://doi.org/10.1109/dft56152.2022.9962352openalex-snapshot
Is RISC-V ready for Space? A Security Perspective
inferred← citeshttps://doi.org/10.1109/dmc58182.2023.10412465openalex-snapshot
Virtual Prototyping of PLCs for Fault Prediction and Optimization
inferred← citeshttps://doi.org/10.1109/dsc47296.2019.8937682openalex-snapshot
Defeating Speculative-Execution Attacks on SGX with HyperRace
inferred← citeshttps://doi.org/10.1109/dsd60849.2023.00066openalex-snapshot
Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00027openalex-snapshot
Securing Elapsed Time for Blockchain: Proof of Hardware Time and Some of its Physical Threats
inferred← citeshttps://doi.org/10.1109/dsn64029.2025.00053openalex-snapshot
Valkyrie: A Response Framework to Augment Runtime Detection of Time-Progressive Attacks
inferred← citeshttps://doi.org/10.1109/eit68936.2026.11670380openalex-snapshot
Security in Asynchronous Circuits: A Review of Side-Channel Attacks and Hardware Trojan Threats
inferred← citeshttps://doi.org/10.1109/ets69887.2026.11591831openalex-snapshot
A real opportunity or still a promise? The current status of the RISC-V ecosystem
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00041openalex-snapshot
Nonce@Once: A Single-Trace EM Side Channel Attack on Several Constant-Time Elliptic Curve Implementations in Mobile Platforms
inferred← citeshttps://doi.org/10.1109/eurosp51992.2021.00047openalex-snapshot
FastSpec: Scalable Generation and Detection of Spectre Gadgets Using Neural Embeddings
inferred← citeshttps://doi.org/10.1109/eurosp57164.2023.00044openalex-snapshot
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
inferred← citeshttps://doi.org/10.1109/eurosp63326.2025.00065openalex-snapshot
LeapFrog: The Rowhammer Instruction Skip Attack
inferred← citeshttps://doi.org/10.1109/eurosp68448.2026.00062openalex-snapshot
VerIFI: Formal Verification of Microarchitectural Information-Flow Integrity
inferred← citeshttps://doi.org/10.1109/eurospw55150.2022.00057openalex-snapshot
Remotizing and Virtualizing Chips and Circuits for Hardware-based Capture-the-Flag Challenges
inferred← citeshttps://doi.org/10.1109/honet67928.2025.11318511openalex-snapshot
Mitigating DDR4 Timing Side-Channels in FPGA Cloud Platforms
inferred← citeshttps://doi.org/10.1109/host49136.2021.9702278openalex-snapshot
Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning
inferred← citeshttps://doi.org/10.1109/host49136.2021.9702280openalex-snapshot
ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor
inferred← citeshttps://doi.org/10.1109/host49136.2021.9702290openalex-snapshot
iTimed: Cache Attacks on the Apple A10 Fusion SoC
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133344openalex-snapshot
Towards Secure Classical-Quantum Systems
inferred← citeshttps://doi.org/10.1109/host55342.2024.10545393openalex-snapshot
Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database
inferred← citeshttps://doi.org/10.1109/host64725.2025.11050073openalex-snapshot
LAPD: Lifecycle-Aware Power-Based Malware Detection
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00015openalex-snapshot
Abusing Cache Line Dirty States to Leak Information in Commercial Processors
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00012openalex-snapshot
Exploitation of Security Vulnerability on Retirement
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00013openalex-snapshot
GADGETSPINNER: A New Transient Execution Primitive Using the Loop Stream Detector
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00025openalex-snapshot
Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00039openalex-snapshot
SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction
inferred← citeshttps://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00121openalex-snapshot
StatekeepSpec: Securing Speculative Execution via forbidding Change-Of-State
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323688openalex-snapshot
CRYSTALS-Dilithium on RISC-V Processor: Lightweight Secure Boot Using Post-Quantum Digital Signature
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11240966openalex-snapshot
Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces
inferred← citeshttps://doi.org/10.1109/iccad66269.2025.11241011openalex-snapshot
CacheGuardian: A Timing Side-Channel Resilient LLC Design
inferred← citeshttps://doi.org/10.1109/iccd50377.2020.00021openalex-snapshot
Special Session: Potentially Leaky Controller: Examining Cache Side-Channel Attacks in Programmable Logic Controllers
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00093openalex-snapshot
Architectural Contracts for Safe Speculation
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00094openalex-snapshot
Execute on Clear (EoC): Enhancing Security for Unsafe Speculative Instructions by Precise Identification and Safe Execution
inferred← citeshttps://doi.org/10.1109/icct62411.2024.10946638openalex-snapshot
Path-specific Information Flow Analysis for RSA Hardware Timing Channel Security Verification
inferred← citeshttps://doi.org/10.1109/iccws48432.2020.9292371openalex-snapshot
Hardware-Assisted Isolation Technologies: Security Architecture and Vulnerability Analysis
inferred← citeshttps://doi.org/10.1109/icdis55630.2022.00014openalex-snapshot
Attacking Malware Detection using Adversarial Machine Learning
inferred← citeshttps://doi.org/10.1109/icicm63644.2024.10814454openalex-snapshot
An Automatic Extraction and Verification Method of Security Properties for Integrated Circuit Design
inferred← citeshttps://doi.org/10.1109/icsc63108.2024.10895397openalex-snapshot
L1TF Foreshadow CPU Vulnerabilities Analysis and Mitigation
inferred← citeshttps://doi.org/10.1109/icsme64153.2025.00044openalex-snapshot
Security Vulnerabilities in Docker Images: A Cross-Tag Study of Application Dependencies
inferred← citeshttps://doi.org/10.1109/iiswc50251.2020.00020openalex-snapshot
High Frequency Performance Monitoring via Architectural Event Measurement
inferred← citeshttps://doi.org/10.1109/iolts65288.2025.11117010openalex-snapshot
On Post-Quantum Attribute-Based Encryption for Automotive Over-the-Air Software Updates
inferred← citeshttps://doi.org/10.1109/iolts69666.2026.11633725openalex-snapshot
Exploring microarchitectural information from SoC communication buses to detect firmware corruption
inferred← citeshttps://doi.org/10.1109/iolts69666.2026.11633860openalex-snapshot
Reality Check for RISC-V: Assessing Software Maturity, Performance and Security
inferred← citeshttps://doi.org/10.1109/ipdps64566.2025.00099openalex-snapshot
CoRD: Converged RDMA Dataplane
inferred← citeshttps://doi.org/10.1109/isdfs69419.2026.11459082openalex-snapshot
Microarchitectural Espionage: FPGA-Based Security Analysis of Branch Prediction in RISC-V Out-of-Order Cores
inferred← citeshttps://doi.org/10.1109/ised67359.2025.11404976openalex-snapshot
SideSec: Detecting and Mitigating Microarchitectural Side-Channel Attacks in Cloud VMs via Entropy Monitoring and Dynamic VM Reallocation
inferred← citeshttps://doi.org/10.1109/ispa-bdcloud-socialcom-sustaincom51426.2020.00071openalex-snapshot
Atomic Restriction: Hardware Atomization to Defend Against Preemption Attacks
inferred← citeshttps://doi.org/10.1109/isqed60706.2024.10528744openalex-snapshot
TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments
inferred← citeshttps://doi.org/10.1109/isqed69900.2026.11534697openalex-snapshot
Trusted Memory Access Monitoring (TMAM): Detecting Fine-Grained DDR4 Access Patterns in FPGA Clouds
inferred← citeshttps://doi.org/10.1109/itc-asia71864.2026.11710822openalex-snapshot
ContextFuzz: A Framework for Discovering Speculative Fetch Attacks
inferred← citeshttps://doi.org/10.1109/itc-asia71864.2026.11710838openalex-snapshot
CPCRFuzz: Adaptive Security-Critical Path and Control-Register Guided Fuzzing for Processor Vulnerability Detection
inferred← citeshttps://doi.org/10.1109/lca.2025.3544989openalex-snapshot
Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
inferred← citeshttps://doi.org/10.1109/lca.2025.3555183openalex-snapshot
Exploiting Intel AMX Power Gating
inferred← citeshttps://doi.org/10.1109/les.2024.3513638openalex-snapshot
Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II
inferred← citeshttps://doi.org/10.1109/mc.2024.3434848openalex-snapshot
Formal Verification for Secure Processors: A Guide for Computer Architects
inferred← citeshttps://doi.org/10.1109/mcom.001.1900632openalex-snapshot
Vessels Cybersecurity: Issues, Challenges, and the Road Ahead
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00088openalex-snapshot
Veiled Pathways: Investigating Covert and Side Channels Within GPU Uncore
inferred← citeshttps://doi.org/10.1109/milcom61039.2024.10773698openalex-snapshot
Analyzing Cache Timing-based Side Channel Vulnerability through Cache Line Composition
inferred← citeshttps://doi.org/10.1109/mm.2021.3069158openalex-snapshot
Leaking Secrets Through Compressed Caches
inferred← citeshttps://doi.org/10.1109/mm.2023.3273189openalex-snapshot
PACMAN: Attacking ARM Pointer Authentication With Speculative Execution
inferred← citeshttps://doi.org/10.1109/msec.2021.3055799openalex-snapshot
Understanding the Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
inferred← citeshttps://doi.org/10.1109/msec.2023.3299349openalex-snapshot
Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/ojcs.2025.3591359openalex-snapshot
Simulators for Processors Used in Virtualization: A Survey
inferred← citeshttps://doi.org/10.1109/pact58117.2023.00030openalex-snapshot
SpecCheck: A Tool for Systematic Identification of Vulnerable Transient Execution in gem5
inferred← citeshttps://doi.org/10.1109/qce53715.2022.00045openalex-snapshot
Reconstructing quantum circuits through side-channel information on cloud-based superconducting quantum computers
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00011openalex-snapshot
JANUS: A Simple and Efficient Speculative Defense using Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/sbac-pad63648.2024.00027openalex-snapshot
S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks
inferred← citeshttps://doi.org/10.1109/seed61283.2024.00013openalex-snapshot
Channelizer: Explainable ML Inference for Validating Side-Channel Resistant Systems
inferred← citeshttps://doi.org/10.1109/socc58585.2023.10256845openalex-snapshot
M-Party: A Secure Dynamic Cache Partitioning by More Than Two Parties
inferred← citeshttps://doi.org/10.1109/southeastcon52093.2024.10500257openalex-snapshot
A Taxonomy of Side-Channels
inferred← citeshttps://doi.org/10.1109/sp40001.2021.00020openalex-snapshot
CrossTalk: Speculative Data Leaks Across Cores Are Real
inferred← citeshttps://doi.org/10.1109/sp46214.2022.9833802openalex-snapshot
SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179368openalex-snapshot
SQUIP: Exploiting the Scheduler Queue Contention Side Channel
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179433openalex-snapshot
WarpAttack: Bypassing CFI through Compiler-Introduced Double-Fetches
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179472openalex-snapshot
SecureCells: A Secure Compartmentalized Architecture
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00048openalex-snapshot
Serberus: Protecting Cryptographic Code from Spectres at Compile-Time
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00058openalex-snapshot
Shedding Light on CVSS Scoring Inconsistencies: A User-Centric Study on Evaluating Widespread Security Vulnerabilities
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00062openalex-snapshot
BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00116openalex-snapshot
Janus: Safe Biometric Deduplication for Humanitarian Aid Distribution
inferred← citeshttps://doi.org/10.1109/sp54263.2024.00268openalex-snapshot
SoK: A Comprehensive Analysis and Evaluation of Docker Container Attack and Defense Mechanisms
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00039openalex-snapshot
Tiktag: Breaking ARM's Memory Tagging Extension with Speculative Execution
inferred← citeshttps://doi.org/10.1109/sp61157.2025.00075openalex-snapshot
SoK: Software Compartmentalization
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00007openalex-snapshot
Enter, Exit, Page Fault, Leak ${ }^{\ddagger}$: Testing Isolation Boundaries for Microarchitectural Leaks
inferred← citeshttps://doi.org/10.1109/sp63933.2026.00231openalex-snapshot
NanoTag: Systems Support for Efficient Byte-Granular Overflow Detection on ARM MTE
inferred← citeshttps://doi.org/10.1109/spw67851.2025.00012openalex-snapshot
Hi-Res: Precise Exploit Detection Using Object-Granular Memory Monitoring
inferred← citeshttps://doi.org/10.1109/tc.2024.3521225openalex-snapshot
Microarchitectural Attacks and Mitigations on Retire Resources in Modern Processors
inferred← citeshttps://doi.org/10.1109/tcad.2025.3527903openalex-snapshot
Oxpecker: Leaking Secrets via Fetch Target Queue
inferred← citeshttps://doi.org/10.1109/tce.2023.3323621openalex-snapshot
BTIDEC: A Novel Detection Scheme for CPU Security of Consumer Electronics
inferred← citeshttps://doi.org/10.1109/tdsc.2026.3678915openalex-snapshot
InStorm: An Instruction-Level Vulnerability Testing Framework for Graphics Processing Units
inferred← citeshttps://doi.org/10.1109/tetc.2023.3271315openalex-snapshot
A Large Scale Characterization of Device Uptimes
inferred← citeshttps://doi.org/10.1109/tifs.2025.3583490openalex-snapshot
RevokAll: Hardware-Assisted Revocable Data Sharing Framework for Full Data Traffic With Rapid Deployment in Cloud-Edge
inferred← citeshttps://doi.org/10.1109/tii.2020.3047416openalex-snapshot
ContainerGuard: A Real-Time Attack Detection System in Container-Based Big Data Platform
inferred← citeshttps://doi.org/10.1109/trustcom50675.2020.00052openalex-snapshot
TEADS: A Defense-Aware Framework for Synthesizing Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/trustcom50675.2020.00059openalex-snapshot
Partial-SMT: Core-Scheduling Protection Against SMT Contention-Based Attacks
inferred← citeshttps://doi.org/10.1109/trustcom50675.2020.00253openalex-snapshot
AndroTIME: Identifying Timing Side Channels in the Android API
inferred← citeshttps://doi.org/10.1109/trustcom60117.2023.00131openalex-snapshot
Flush+Revisit: A Cross-CCX Side-Channel Attack on AMD Processors
inferred← citeshttps://doi.org/10.1109/trustcom63139.2024.00082openalex-snapshot
You Are as You Type: Investigating the Influence of Timestamp Accuracy on the Robustness of Keystroke Biometrics
inferred← citeshttps://doi.org/10.1109/trustcom63139.2024.00204openalex-snapshot
Secure Join and Compute in Encrypted Database
inferred← citeshttps://doi.org/10.1109/tsc.2025.3539189openalex-snapshot
SHELDB: Client Storage Aware Homomorphic Encrypted Database Processing Framework With Low Communication Overhead
inferred← citeshttps://doi.org/10.1109/tvcg.2021.3114866openalex-snapshot
Visual Analysis of Hyperproperties for Understanding Model Checking Results
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3579484openalex-snapshot
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing
inferred← citeshttps://doi.org/10.1109/vlsi-soc57769.2023.10321922openalex-snapshot
SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors
inferred← citeshttps://doi.org/10.1109/vts56346.2023.10140100openalex-snapshot
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance
inferred← citeshttps://doi.org/10.1117/12.3031239openalex-snapshot
Behavior-based dynamic trusted measurement scheme
inferred← citeshttps://doi.org/10.1145/3508360openalex-snapshot
The Serverless Computing Survey: A Technical Primer for Design Architecture
inferred← citeshttps://doi.org/10.1145/3514105.3514112openalex-snapshot
An Evaluation of Meltdown Vulnerability
inferred← citeshttps://doi.org/10.1145/3528082.3544833openalex-snapshot
Implementing ChaCha based crypto primitives on programmable SmartNICs
inferred← citeshttps://doi.org/10.1145/3531063openalex-snapshot
Yoneda Hacking: The Algebra of Attacker Actions
inferred← citeshttps://doi.org/10.1145/3560834.3563823openalex-snapshot
Breaking KASLR on Mobile Devices without Any Use of Cache Memory
inferred← citeshttps://doi.org/10.1145/3575693.3575719openalex-snapshot
AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
inferred← citeshttps://doi.org/10.1145/3578357.3589456openalex-snapshot
Resilient and Secure System on Chip with Rejuvenation in the Wake of Persistent Attacks
inferred← citeshttps://doi.org/10.1145/3579371.3589053openalex-snapshot
SHARP: A Short-Word Hierarchical Accelerator for Robust and Practical Fully Homomorphic Encryption
inferred← citeshttps://doi.org/10.1145/3600061.3600063openalex-snapshot
FastWake: Revisiting Host Network Stack for Interrupt-mode RDMA
inferred← citeshttps://doi.org/10.1145/3607199.3607248openalex-snapshot
Quarantine: Mitigating Transient Execution Attacks with Physical Domain Isolation
inferred← citeshttps://doi.org/10.1145/3652597openalex-snapshot
Intel TDX Demystified: A Top-Down Approach
inferred← citeshttps://doi.org/10.1145/3676641.3716274openalex-snapshot
SMaCk: Efficient Instruction Cache Attacks via Self-Modifying Code Conflicts
inferred← citeshttps://doi.org/10.1145/3676642.3736115openalex-snapshot
DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
inferred← citeshttps://doi.org/10.1145/3678890.3678907openalex-snapshot
VeriFence: Lightweight and Precise Spectre Defenses for Untrusted Linux Kernel Extensions
inferred← citeshttps://doi.org/10.1145/3689031.3717473openalex-snapshot
A Hardware-Software Co-Design for Efficient Secure Containers
inferred← citeshttps://doi.org/10.1145/3689031.3717490openalex-snapshot
AlloyStack: A Library Operating System for Serverless Workflow Applications
inferred← citeshttps://doi.org/10.1145/3695053.3731119openalex-snapshot
SpecASan: Mitigating Transient Execution Attacks Using Speculative Address Sanitization
inferred← citeshttps://doi.org/10.1145/3696843.3696849openalex-snapshot
SoK Paper: Power Side-Channel Malware Detection
inferred← citeshttps://doi.org/10.1145/3701717.3730543openalex-snapshot
Practical Secure Aggregation by Combining Cryptography and Trusted Execution Environments
inferred← citeshttps://doi.org/10.1145/3715001openalex-snapshot
A Container Security Survey: Exploits, Attacks, and Defenses
inferred← citeshttps://doi.org/10.1145/3719027.3744849openalex-snapshot
BASTAG: Byte-level Access Control on Shared Memory using ARM Memory Tagging Extension
inferred← citeshttps://doi.org/10.1145/3725843.3756097openalex-snapshot
GateBleed: Exploiting On-Core Accelerator Power Gating for High Performance and Stealthy Attacks on AI
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