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Formal verification of high-level synthesis

https://doi.org/10.1145/3485494
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Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/11576280_20openalex-snapshot
Formal Verification of a Memory Model for C-Like Imperative Languages
inferredcites →https://doi.org/10.1007/978-3-540-70545-1_44openalex-snapshot
Validating High-Level Synthesis
inferredcites →https://doi.org/10.1007/978-3-642-28869-2_20openalex-snapshot
Validating LR(1) Parsers
inferredcites →https://doi.org/10.1007/bfb0054170openalex-snapshot
Translation validation
inferredcites →https://doi.org/10.1007/s00236-011-0142-yopenalex-snapshot
Correct hardware synthesis
inferredcites →https://doi.org/10.1007/s10817-018-9496-yopenalex-snapshot
CompCertS: A Memory-Aware Verified C Compiler Using a Pointer as Integer Semantics
inferredcites →https://doi.org/10.1016/j.scico.2010.02.007openalex-snapshot
Mechanised wire-wise verification of Handel-C synthesis
inferredcites →https://doi.org/10.1109/asap.2016.7760777openalex-snapshot
Synthesisable recursion for C++ HLS tools
inferredcites →https://doi.org/10.1109/codes-isss.2013.6659002openalex-snapshot
Improving polyhedral code generation for high-level synthesis
inferredcites →https://doi.org/10.1109/date.1999.761092openalex-snapshot
FSMD functional partitioning for low power
inferredcites →https://doi.org/10.1109/edac.1992.205894openalex-snapshot
Verified high-level synthesis in BEDROC
inferredcites →https://doi.org/10.1109/fccm.2008.46openalex-snapshot
Kiwi: Synthesis of FPGA Circuits from Parallel Programs
inferredcites →https://doi.org/10.1109/fccm51124.2021.00034openalex-snapshot
An Empirical Study of the Reliability of High-Level Synthesis Tools
inferredcites →https://doi.org/10.1109/formalise.2019.00020openalex-snapshot
A Proof-Producing Translator for Verilog Development in HOL
inferredcites →https://doi.org/10.1109/fpl.2013.6645550openalex-snapshot
Bambu: A modular framework for the high level synthesis of memory-intensive applications
inferredcites →https://doi.org/10.1109/iccad.2007.4397305openalex-snapshot
Operation chaining asynchronous pipelined circuits
inferredcites →https://doi.org/10.1109/iccad.2017.8203809openalex-snapshot
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
inferredcites →https://doi.org/10.1109/ieeestd.2005.339572openalex-snapshot
Verilog Register Transfer Level Synthesis
inferredcites →https://doi.org/10.1109/ieeestd.2006.99495openalex-snapshot
IEEE Standard for Verilog Hardware Description Language
inferredcites →https://doi.org/10.1109/isqed.2004.1283659openalex-snapshot
Automated formal verification of scheduling process using finite state machines with datapath (FSMD)
inferredcites →https://doi.org/10.1109/isqed.2006.10openalex-snapshot
A Formal Verification Method of Scheduling in High-level Synthesis
inferredcites →https://doi.org/10.1109/memcod.2004.1459818openalex-snapshot
Lbtorial bluespec systemverilog: efficient, correct RTL from high-level specifications
inferredcites →https://doi.org/10.1109/memcod.2010.5558634openalex-snapshot
A formal executable semantics of Verilog
inferredcites →https://doi.org/10.1109/reconfig.2014.7032504openalex-snapshot
Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study
inferredcites →https://doi.org/10.1109/reconfig.2017.8279807openalex-snapshot
Rapid circuit-specific inlining tuning for FPGA high-level synthesis
inferredcites →https://doi.org/10.1109/samos.2016.7818341openalex-snapshot
Design productivity of a high level synthesis compiler versus HDL
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2014.2314392openalex-snapshot
Verification of Code Motion Techniques Using Value Propagation
inferredcites →https://doi.org/10.1109/tcad.2018.2846654openalex-snapshot
Translation Validation of Code Motion Transformations Involving Loops
inferredcites →https://doi.org/10.1109/tvlsi.2020.2978242openalex-snapshot
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
inferredcites →https://doi.org/10.1145/1328438.1328444openalex-snapshot
Formal verification of translation validators
inferredcites →https://doi.org/10.1145/1538788.1538814openalex-snapshot
Formal verification of a realistic compiler
inferredcites →https://doi.org/10.1145/1837274.1837489openalex-snapshot
What input-language is the best choice for high level synthesis (HLS)?
inferredcites →https://doi.org/10.1145/1950413.1950423openalex-snapshot
LegUp
inferredcites →https://doi.org/10.1145/1993498.1993532openalex-snapshot
Finding and understanding bugs in C compilers
inferredcites →https://doi.org/10.1145/2103656.2103709openalex-snapshot
Formalizing the LLVM intermediate representation for verified program transformations
inferredcites →https://doi.org/10.1145/2228360.2228584openalex-snapshot
Chisel
inferredcites →https://doi.org/10.1145/2435264.2435273openalex-snapshot
Polyhedral-based data reuse optimization for configurable computing
inferredcites →https://doi.org/10.1145/2487241.2487248openalex-snapshot
CompCertTSO
inferredcites →https://doi.org/10.1145/2737924.2737986openalex-snapshot
Many-core compiler fuzzing
inferredcites →https://doi.org/10.1145/3192366.3192379openalex-snapshot
Spatial: a language and compiler for application accelerators
inferredcites →https://doi.org/10.1145/3240765.3240815openalex-snapshot
HLS-based optimization and design space exploration for applications with variable loop bounds
inferredcites →https://doi.org/10.1145/3314221.3314622openalex-snapshot
Verified compilation on a verified processor
inferredcites →https://doi.org/10.1145/3385412.3385965openalex-snapshot
The essence of Bluespec: a core language for rule-based hardware design
inferredcites →https://doi.org/10.1145/3385412.3385974openalex-snapshot
Predictable accelerator design with time-sensitive affine types
inferredcites →https://doi.org/10.1145/3385412.3386024openalex-snapshot
LLHD: a multi-level intermediate representation for hardware description languages
inferredcites →https://doi.org/10.1145/3428197openalex-snapshot
Certified and efficient instruction scheduling: application to interlocked VLIW processors
inferredcites →https://doi.org/10.1145/3428265openalex-snapshot
CompCertELF: verified separate compilation of C programs into ELF object files
inferredcites →https://doi.org/10.1145/3437992.3439916openalex-snapshot
Lutsig: a verified Verilog compiler for verified circuit development
inferredcites →https://doi.org/10.1145/74382.74383openalex-snapshot
Scheduling and binding algorithms for high-level synthesis
inferredcites →https://doi.org/10.1145/775832.775928openalex-snapshot
Behavioral consistency of C and verilog programs using bounded model checking
inferredcites →https://doi.org/10.5281/zenodo.3983572openalex-snapshot
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What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-13074-8_16openalex-snapshot
Machine Learning for Agile FPGA Design
inferred← citeshttps://doi.org/10.1007/978-3-031-57259-3openalex-snapshot
Fundamental Approaches to Software Engineering
inferred← citeshttps://doi.org/10.1007/978-3-031-57259-3_1openalex-snapshot
From Mechanized Semantics to Verified Compilation: the Clight Semantics of CompCert
inferred← citeshttps://doi.org/10.1007/978-3-031-97492-2_10openalex-snapshot
Verification of Concurrent Programs Using Hybrid Concrete-Symbolic Interpretation
inferred← citeshttps://doi.org/10.1109/access.2024.3414374openalex-snapshot
FABI: A Formal Analyzer of Binary Image Objects Identification Tools
inferred← citeshttps://doi.org/10.1109/access.2025.3540320openalex-snapshot
High-Level Synthesis for FPGAs—A Hardware Engineer’s Perspective
inferred← citeshttps://doi.org/10.1109/access.2025.3605852openalex-snapshot
AnnotationGym: A Generic Framework for Automatic Source Code Annotation
inferred← citeshttps://doi.org/10.1109/async58294.2023.10239640openalex-snapshot
Verification-Driven Design for Asynchronous VLSI
inferred← citeshttps://doi.org/10.1109/csf57540.2023.00029openalex-snapshot
A Generic Framework to Develop and Verify Security Mechanisms at the Microarchitectural Level: Application to Control-Flow Integrity
inferred← citeshttps://doi.org/10.1109/dac56929.2023.10247880openalex-snapshot
Lightning Talk: The Next Wave of High-level Synthesis
inferred← citeshttps://doi.org/10.1109/dft59622.2023.10313550openalex-snapshot
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis
inferred← citeshttps://doi.org/10.1109/fccm53951.2022.9786208openalex-snapshot
Resource Sharing for Verified High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323796openalex-snapshot
Automatic Inductive Invariant Generation for Scalable Dataflow Circuit Verification
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00062openalex-snapshot
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3437992.3439916openalex-snapshot
Lutsig: a verified Verilog compiler for verified circuit development
inferred← citeshttps://doi.org/10.1145/3591234openalex-snapshot
Modular Hardware Design with Timeline Types
inferred← citeshttps://doi.org/10.1145/3622805openalex-snapshot
The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog
inferred← citeshttps://doi.org/10.1145/3656455openalex-snapshot
Hyperblock Scheduling for Verified High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3676641.3715993openalex-snapshot
ElasticMiter: Formally Verified Dataflow Circuit Rewrites
inferred← citeshttps://doi.org/10.1145/3706628.3708872openalex-snapshot
Latency Insensitivity Testing for Dataflow HLS Designs
inferred← citeshttps://doi.org/10.1145/3715325openalex-snapshot
Unveiling Cross-checking Opportunities in Verilog Compilers
inferred← citeshttps://doi.org/10.1145/3720432openalex-snapshot
A Mechanized Semantics for Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3729331openalex-snapshot
Making Concurrent Hardware Verification Sequential
inferred← citeshttps://doi.org/10.1145/3748173.3779185openalex-snapshot
Finding and Understanding Bugs in FPGA Place-and-Route Engines
inferred← citeshttps://doi.org/10.1145/3779031.3779091openalex-snapshot
A Rose Tree Is Blooming (Proof Pearl)
inferred← citeshttps://doi.org/10.1145/3779212.3790166openalex-snapshot
Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits
inferred← citeshttps://doi.org/10.1145/3785652openalex-snapshot
Lessons from Formally Verified Deployed Software Systems
inferred← citeshttps://doi.org/10.1145/3808263openalex-snapshot
Let It Flow: A Formally Verified Compilation Framework for Asynchronous Dataflow
inferred← citeshttps://doi.org/10.70675/8640ad41zfb4fz40ecz8e27z200801a72369openalex-snapshot
Formal Specification and Verification of Security Mechanisms for RISC-V Processors
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