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A Survey on Thwarting Memory Corruption in RISC-V
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Hardware Assisted Randomization of Data
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Detection of Intrusions and Malware, and Vulnerability Assessment
inferredcites →https://doi.org/10.1007/978-3-642-34961-4_14openalex-snapshot
PRINCE – A Low-Latency Block Cipher for Pervasive Computing Applications
inferredcites →https://doi.org/10.1007/s11390-020-9703-2openalex-snapshot
IMPULP: A Hardware Approach for In-Process Memory Protection via User-Level Partitioning
inferredcites →https://doi.org/10.1016/j.compeleceng.2013.11.011openalex-snapshot
Secure embedded system hardware design – A flexible security and trust enhanced approach
inferredcites →https://doi.org/10.1016/j.jnca.2020.102534openalex-snapshot
A Survey of Exploitation Techniques and Defenses for Program Data Attacks
inferredcites →https://doi.org/10.1109/access.2019.2920176openalex-snapshot
DOPdefenderPlus: A Data-Oriented Programming Attack Mitigation Technique for Complex Software
inferredcites →https://doi.org/10.1109/ancs.2011.32openalex-snapshot
Non-crypto Hardware Hash Functions for High Performance Networking ASICs
inferredcites →https://doi.org/10.1109/apsec48747.2019.00036openalex-snapshot
Dam: A Practical Scheme to Mitigate Data-Oriented Attacks with Tagged Memory Based on Hardware
inferredcites →https://doi.org/10.1109/dsd.2018.00093openalex-snapshot
CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity
inferredcites →https://doi.org/10.1109/eurosp.2018.00023openalex-snapshot
Sponge-Based Control-Flow Protection for IoT Devices
inferredcites →https://doi.org/10.1109/hpec.2018.8547578openalex-snapshot
Design and Implementation of a Dynamic Information Flow Tracking Architecture to Secure a RISC-V Core for IoT Applications
inferredcites →https://doi.org/10.1109/iaeac.2018.8577547openalex-snapshot
A Control Flow Integrity Checking Technique Based on Hardware Support
inferredcites →https://doi.org/10.1109/isca.2014.6853201openalex-snapshot
The CHERI capability model: Revisiting RISC in an age of risk
inferredcites →https://doi.org/10.1109/jproc.2019.2918437openalex-snapshot
Edge Computing Security: State of the Art and Challenges
inferredcites →https://doi.org/10.1109/mm.2019.2897677openalex-snapshot
On the Spectre and Meltdown Processor Security Vulnerabilities
inferredcites →https://doi.org/10.1109/msp.2011.67openalex-snapshot
Stuxnet: Dissecting a Cyberwarfare Weapon
inferredcites →https://doi.org/10.1109/mtv48867.2019.00018openalex-snapshot
Hardware and Software Co-Verification from Security Perspective
inferredcites →https://doi.org/10.1109/patmos.2017.8106976openalex-snapshot
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
inferredcites →https://doi.org/10.1109/secdev.2019.00022openalex-snapshot
Exploitation Techniques and Defenses for Data-Oriented Attacks
inferredcites →https://doi.org/10.1109/sp.2016.9openalex-snapshot
HDFI: Hardware-Assisted Data-Flow Isolation
inferredcites →https://doi.org/10.1109/tc.2018.2807818openalex-snapshot
ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits
inferredcites →https://doi.org/10.1109/tcad.2018.2857321openalex-snapshot
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators
inferredcites →https://doi.org/10.1109/tcad.2020.2984407openalex-snapshot
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V
inferredcites →https://doi.org/10.1109/trustcom/bigdatase.2018.00083openalex-snapshot
TMDFI: Tagged Memory Assisted for Fine-Grained Data-Flow Integrity Towards Embedded Systems Against Software Exploitation
inferredcites →https://doi.org/10.1145/1024393.1024404openalex-snapshot
Secure program execution via dynamic information flow tracking
inferredcites →https://doi.org/10.1145/1029894.1029911openalex-snapshot
Testing static analysis tools using exploitable buffer overflows from open source code
inferredcites →https://doi.org/10.1145/1842733.1842748openalex-snapshot
Pointer tainting still pointless
inferredcites →https://doi.org/10.1145/3224423openalex-snapshot
Intel MPX Explained: A Cross-layer Analysis of the Intel MPX System Stack
inferredcites →https://doi.org/10.1145/3316482.3326356openalex-snapshot
SHAKTI-MS: a RISC-V processor for memory safety in C
inferredcites →https://doi.org/10.1145/3371307.3371311openalex-snapshot
Preventing zero-day exploits of memory vulnerabilities with guard lines
inferredcites →https://doi.org/10.1145/3457388.3458657openalex-snapshot
A comparative survey of open-source application-class RISC-V processor implementations
inferredcites →https://doi.org/10.23919/date.2019.8714980openalex-snapshot
FIXER: Flow Integrity Extensions for Embedded RISC-V
inferredcites →https://doi.org/10.3390/electronics10172068openalex-snapshot
A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V
inferredcites →https://doi.org/10.46586/tosc.v2017.i1.4-44openalex-snapshot
The QARMA Block Cipher Family. Almost MDS Matrices Over Rings With Zero Divisors, Nearly Symmetric Even-Mansour Constructions With Non-Involutory Central Rounds, and Search Heuristics for Low-Latency S-Boxes
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1016/j.cose.2025.104817openalex-snapshot
Attacks, defenses and perspectives for the runtime security of RISC-V IoT devices: A review
inferred← citeshttps://doi.org/10.1016/j.iot.2025.101513openalex-snapshot
LWSEE: Lightweight Secured Software-Based Execution Environment
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103943openalex-snapshot
SeSBI: A formally specified RISC-V SBI firmware with hierarchical verification
inferred← citeshttps://doi.org/10.1109/access.2025.3610616openalex-snapshot
Binary Code Analysis for Cybersecurity: A Systematic Review of Forensic Techniques in Vulnerability Detection and Anti-Evasion Strategies
inferred← citeshttps://doi.org/10.1109/acsac67867.2025.00035openalex-snapshot
PSan: Towards Hybrid Metadata Scheme for Efficient Pointer Checking
inferred← citeshttps://doi.org/10.1109/cipher70417.2026.11523931openalex-snapshot
Hardware-Software Co-design Implementation of 32 bit RISC V
inferred← citeshttps://doi.org/10.1109/ddecs63720.2025.11006772openalex-snapshot
S4V: A Benchmark Suite of Transient Execution Attacks for RISC-V Processors
inferred← citeshttps://doi.org/10.1109/ddecs69233.2026.11521000openalex-snapshot
Assessing the Vulnerability of Open-Source RISC-V Processors to Transient Execution Attacks
inferred← citeshttps://doi.org/10.1109/icoici62503.2024.10696057openalex-snapshot
RISC-V Power Analysis Attack Mitigation in a GPU Execution Framework
inferred← citeshttps://doi.org/10.1109/indiscon66021.2025.11252023openalex-snapshot
A Security Framework for RISC-V SoC using Hardware Software Co-Design
inferred← citeshttps://doi.org/10.1109/issre66568.2025.00024openalex-snapshot
ShadowGuard: Cryptographic Shadow Stack Protection with XOR Obfuscation and HMAC Integrity
inferred← citeshttps://doi.org/10.1145/3694848.3694854openalex-snapshot
MiniJava on RISC-V: A Game of Global Compilers Domination
inferred← citeshttps://doi.org/10.1145/3814942.3816133openalex-snapshot
Interpreter Memory Safety via Differential Fuzzing with a CHERI on Top
inferred← citeshttps://doi.org/10.30970/eli.24.6openalex-snapshot
CONSTRUCTION OF A SMART ENTERPRISE MANAGEMENT SYSTEM USING WEAK SIGNALS
inferred← citeshttps://doi.org/10.3390/app16136436openalex-snapshot
A Scoping Review of Composite Evaluation Approaches for Software Architectures on Resource-Constrained Hardware
inferred← citeshttps://doi.org/10.3390/chips5030024openalex-snapshot
RISC-Based Secure Architecture for Data-Flow Integrity in Modern Embedded and Edge Systems
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