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C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap

https://doi.org/10.1145/3734524
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/iccd46524.2019.00054openalex-snapshot
Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow
inferredcites →https://doi.org/10.1109/iseda62518.2024.10618053openalex-snapshot
ChatChisel: Enabling Agile Hardware Design with Large Language Models
inferredcites →https://doi.org/10.1109/lad62341.2024.10691856openalex-snapshot
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
inferredcites →https://doi.org/10.1109/mlcad58807.2023.10299874openalex-snapshot
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
inferredcites →https://doi.org/10.1109/sp46214.2022.9833571openalex-snapshot
Asleep at the Keyboard? Assessing the Security of GitHub Copilot’s Code Contributions
inferredcites →https://doi.org/10.1109/tcad.2015.2513673openalex-snapshot
A Survey and Evaluation of FPGA High-Level Synthesis Tools
inferredcites →https://doi.org/10.1145/3643681openalex-snapshot
VeriGen: A Large Language Model for Verilog Code Generation
inferredcites →https://doi.org/10.1145/3670474.3685953openalex-snapshot
Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1109/access.2026.3665894openalex-snapshot
A Critical Review and Evaluation of LLMs for RTL Generation
inferred← citeshttps://doi.org/10.1109/icdsbs69077.2026.11635016openalex-snapshot
AI-Powered Automated Verilog Generation and Simulation for Semiconductor Design
inferred← citeshttps://doi.org/10.1109/jetcas.2025.3575272openalex-snapshot
Generative AI Through CAS Lens: An Integrated Overview of Algorithmic Optimizations, Architectural Advances, and Automated Designs
inferred← citeshttps://doi.org/10.1109/mlcad65511.2025.11189130openalex-snapshot
Prompting for Power: Benchmarking Large Language Models for Low-Power RTL Design Generation
inferred← citeshttps://doi.org/10.1109/socc66126.2025.11235352openalex-snapshot
Large Language Models (LLMs) for Electronic Design Automation (EDA) : Special Session Paper
inferred← citeshttps://doi.org/10.1109/vlsitsa69131.2026.11527975openalex-snapshot
A LLM-Assisted High-Level Synthesis Code Transformation from C++ to SystemC
inferred← citeshttps://doi.org/10.1109/vts69484.2026.11563321openalex-snapshot
LLM4SecurePQC: LLM-Driven and Side-Channel Resilient Hardware Synthesis of PQC Cores
inferred← citeshttps://doi.org/10.1145/3749986openalex-snapshot
HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3801487.3806068openalex-snapshot
LLM-Driven Optimization for High-Level Synthesis
inferred← citeshttps://doi.org/10.1145/3829373openalex-snapshot
VTR-LLM: Multi-Agent LLM Framework for Automated Debugging of FPGA CAD Flows
inferred← citeshttps://doi.org/10.1615/jmachlearnmodelcomput.2025058957openalex-snapshot
LLM BENCHMARKING WITH LLaMA2: EVALUATING CODE DEVELOPMENT PERFORMANCE ACROSS MULTIPLE PROGRAMMING LANGUAGES
inferred← citeshttps://doi.org/10.2139/ssrn.6926957openalex-snapshot
The Physical Feedback Loop in LLM-Assisted Embedded Development: A Dual Case Study of Human Roles and Bug Patterns
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539180openalex-snapshot
Focus Session: Stepping Stones Towards Domain Acceleration Using AI-Driven High-Level Synthesis Design
inferred← citeshttps://doi.org/10.23919/date69613.2026.11539440openalex-snapshot
Focus Session: LLM4PQC – Accurate and Efficient Synthesis of PQC Cores by Feedback-Driven LLMs
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