On the public citation graph
Automatic fence insertion for shared memory multiprocessing
0 signed · 95 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11596110_12openalex-snapshot
Automatic Implementation of Programming Language Consistency Models
inferredcites →https://doi.org/10.1017/cbo9780511811432openalex-snapshot
Modern Compiler Implementation in Java
inferredcites →https://doi.org/10.1109/12.947002openalex-snapshot
Hiding relaxed memory consistency with a compiler
inferredcites →https://doi.org/10.1109/mc.1986.1663275openalex-snapshot
1986 International Conference on Parallel Processing
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1109/tc.1987.5009454openalex-snapshot
On Reducing Data Synchronization in Multiprocessed Loops
inferredcites →https://doi.org/10.1109/tc.1987.5009499openalex-snapshot
Compiler Algorithms for Synchronization
inferredcites →https://doi.org/10.1145/17356.17406openalex-snapshot
Memory access buffering in multiprocessors
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/325164.325100openalex-snapshot
Weak ordering---a new definition
inferredcites →https://doi.org/10.1145/325164.325102openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/327070.327266openalex-snapshot
A technique for reducing synchronization overhead in large scale multiprocessors
inferredcites →https://doi.org/10.1145/42190.42277openalex-snapshot
Efficient and correct execution of parallel programs that share memory
inferredcites →https://doi.org/10.26226/morressier.60c8d83cbea1445efd9a1905openalex-snapshot
Cambridge University Press
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11532378_16openalex-snapshot
Efficient Computation of Communicator Variables for Programs with Unstructured Parallelism
inferred← citeshttps://doi.org/10.1007/11817963_45openalex-snapshot
Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study
inferred← citeshttps://doi.org/10.1007/978-3-030-30923-7_9openalex-snapshot
Extracting Safe Thread Schedules from Incomplete Model Checking Results
inferred← citeshttps://doi.org/10.1007/978-3-030-63461-2_16openalex-snapshot
Lock and Fence When Needed: State Space Exploration + Static Analysis = Improved Fence and Lock Insertion
inferred← citeshttps://doi.org/10.1007/978-3-031-19992-9_6openalex-snapshot
Fence Synthesis Under the C11 Memory Model
inferred← citeshttps://doi.org/10.1007/978-3-319-19249-9_19openalex-snapshot
Property-Driven Fence Insertion Using Reorder Bounded Model Checking
inferred← citeshttps://doi.org/10.1007/978-3-319-29817-7_13openalex-snapshot
Weak Memory Models as LLVM-to-LLVM Transformations
inferred← citeshttps://doi.org/10.1007/978-3-319-59647-1_11openalex-snapshot
Locality and Singularity for Store-Atomic Memory Models
inferred← citeshttps://doi.org/10.1007/978-3-540-69330-7_12openalex-snapshot
Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler
inferred← citeshttps://doi.org/10.1007/978-3-540-70545-1_12openalex-snapshot
Effective Program Verification for Relaxed Memory Models
inferred← citeshttps://doi.org/10.1007/978-3-540-79561-2_7openalex-snapshot
Incorporation of OpenMP Memory Consistency into Conventional Dataflow Analysis
inferred← citeshttps://doi.org/10.1007/978-3-642-22110-1_6openalex-snapshot
Stability in Weak Memory Models
inferred← citeshttps://doi.org/10.1007/978-3-642-22306-8_10openalex-snapshot
A Verification-Based Approach to Memory Fence Insertion in Relaxed Memory Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-28756-5_15openalex-snapshot
Counter-Example Guided Fence Insertion under TSO
inferred← citeshttps://doi.org/10.1007/978-3-642-36742-7_24openalex-snapshot
A Verification-Based Approach to Memory Fence Insertion in PSO Memory Systems
inferred← citeshttps://doi.org/10.1007/s10009-020-00575-yopenalex-snapshot
Extracting safe thread schedules from incomplete model checking results
inferred← citeshttps://doi.org/10.1007/s10703-011-0131-3openalex-snapshot
Verification of STM on relaxed memory models
inferred← citeshttps://doi.org/10.1007/s10766-011-0176-3openalex-snapshot
Efficient Sequential Consistency Using Conditional Fences
inferred← citeshttps://doi.org/10.1016/j.scico.2019.04.003openalex-snapshot
A formal model of data access for multicore architectures with multilevel caches
inferred← citeshttps://doi.org/10.1109/acsd.2013.8openalex-snapshot
LTL Model Checking of Parallel Programs with Under-Approximated TSO Memory Model
inferred← citeshttps://doi.org/10.1109/ase.2017.8115688openalex-snapshot
Quick verification of concurrent programs by iteratively relaxed scheduling
inferred← citeshttps://doi.org/10.1109/ase63991.2025.00208openalex-snapshot
Automated Insertion of Flushes and Fences for Persistency
inferred← citeshttps://doi.org/10.1109/cgo.2009.29openalex-snapshot
Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs
inferred← citeshttps://doi.org/10.1109/csf.2014.14openalex-snapshot
Noninterference under Weak Memory Models
inferred← citeshttps://doi.org/10.1109/ipdps.2006.1639272openalex-snapshot
On the effectiveness of speculative and selective memory fences
inferred← citeshttps://doi.org/10.1109/issre.2016.48openalex-snapshot
Detecting, Exposing, and Classifying Sequential Consistency Violations
inferred← citeshttps://doi.org/10.1109/micro.2012.41openalex-snapshot
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically
inferred← citeshttps://doi.org/10.1109/mm.2005.45openalex-snapshot
Computer Architecture: Challenges and Opportunities for the Next Decade
inferred← citeshttps://doi.org/10.1109/pact.2011.70openalex-snapshot
Exploiting Task Order Information for Optimizing Sequentially Consistent Java Programs
inferred← citeshttps://doi.org/10.1109/tpds.2010.172openalex-snapshot
Yet Another Simple Solution for the Concurrent Programming Control Problem
inferred← citeshttps://doi.org/10.1109/tpds.2016.2633353openalex-snapshot
Fence-Free Synchronization with Dynamically Serialized Synchronization Variables
inferred← citeshttps://doi.org/10.1145/1065944.1065947openalex-snapshot
Compiler techniques for high performance sequentially consistent java programs
inferred← citeshttps://doi.org/10.1145/1152154.1152166openalex-snapshot
A two-phase escape analysis for parallel java programs
inferred← citeshttps://doi.org/10.1145/1183401.1183452openalex-snapshot
Lightweight lock-free synchronization methods for multithreading
inferred← citeshttps://doi.org/10.1145/1854273.1854312openalex-snapshot
Efficient sequential consistency using conditional fences
inferred← citeshttps://doi.org/10.1145/1993316.1993521openalex-snapshot
Partial-coherence abstractions for relaxed memory models
inferred← citeshttps://doi.org/10.1145/1993498.1993521openalex-snapshot
Partial-coherence abstractions for relaxed memory models
inferred← citeshttps://doi.org/10.1145/2103621.2103717openalex-snapshot
Clarifying and compiling C/C++ concurrency
inferred← citeshttps://doi.org/10.1145/2103656.2103717openalex-snapshot
Clarifying and compiling C/C++ concurrency
inferred← citeshttps://doi.org/10.1145/2150976.2151006openalex-snapshot
Efficient sequential consistency via conflict ordering
inferred← citeshttps://doi.org/10.1145/2189750.2151006openalex-snapshot
Efficient sequential consistency via conflict ordering
inferred← citeshttps://doi.org/10.1145/2248487.2151006openalex-snapshot
Efficient sequential consistency via conflict ordering
inferred← citeshttps://doi.org/10.1145/2254064.2254115openalex-snapshot
Dynamic synthesis for relaxed memory models
inferred← citeshttps://doi.org/10.1145/2261417.2261436openalex-snapshot
Distributed computing column 46
inferred← citeshttps://doi.org/10.1145/2261417.2261437openalex-snapshot
Automated model repair for distributed programs
inferred← citeshttps://doi.org/10.1145/2261417.2261438openalex-snapshot
Automatic inference of memory fences
inferred← citeshttps://doi.org/10.1145/2345156.2254115openalex-snapshot
Dynamic synthesis for relaxed memory models
inferred← citeshttps://doi.org/10.1145/2688500.2688524openalex-snapshot
Fence placement for legacy data-race-free programs via synchronization read detection
inferred← citeshttps://doi.org/10.1145/2688500.2688552openalex-snapshot
Section based program analysis to reduce overhead of detecting unsynchronized thread communication
inferred← citeshttps://doi.org/10.1145/2766451openalex-snapshot
Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication
inferred← citeshttps://doi.org/10.1145/2786980openalex-snapshot
Leveraging Transactional Execution for Memory Consistency Model Emulation
inferred← citeshttps://doi.org/10.1145/2835179openalex-snapshot
Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection
inferred← citeshttps://doi.org/10.1145/2858788.2688524openalex-snapshot
Fence placement for legacy data-race-free programs via synchronization read detection
inferred← citeshttps://doi.org/10.1145/3192366.3192415openalex-snapshot
Static serializability analysis for causal consistency
inferred← citeshttps://doi.org/10.1145/3296979.3192415openalex-snapshot
Static serializability analysis for causal consistency
inferred← citeshttps://doi.org/10.1145/3445814.3446748openalex-snapshot
VSync: push-button verification and optimization for synchronization primitives on weak memory models
inferred← citeshttps://doi.org/10.1145/3470496.3533045openalex-snapshot
Mixed-proxy extensions for the NVIDIA PTX memory consistency model
inferred← citeshttps://doi.org/10.1145/3508352.3549417openalex-snapshot
Speculative Load Forwarding Attack on Modern Processors
inferred← citeshttps://doi.org/10.48550/arxiv.1703.04603openalex-snapshot
Locality and Singularity for Store-Atomic Memory Models
inferred← citeshttps://doi.org/10.48550/arxiv.1809.01955openalex-snapshot
Safe Execution of Concurrent Programs by Enforcement of Scheduling Constraints
inferred← citeshttps://doi.org/10.5075/epfl-thesis-4541openalex-snapshot
Formalizing and verifying transactional memories
inferred← citeshttps://doi.org/10.5555/1898953.1898968openalex-snapshot
On the effectiveness of speculative and selective memory fences
inferred← citeshttps://doi.org/10.5555/3241639.3241647openalex-snapshot
Characterizing real world bugs causing sequential consistency violations
inferred← citeshttps://doi.org/10.70675/6f86083bz89aez4751zb868zc4ee47a9ccc8openalex-snapshot
Vérification par model-checking de programmes concurrents paramétrés sur des modèles mémoires faibles
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.