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Hardware Security

https://doi.org/10.1201/b17555
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inferred← citeshttps://doi.org/10.1007/978-3-030-12988-0_6openalex-snapshot
Formal Timing Analysis of Digital Circuits
inferred← citeshttps://doi.org/10.1007/978-3-030-71522-9_1712openalex-snapshot
Infective Countermeasure
inferred← citeshttps://doi.org/10.1007/978-3-030-73445-9_1openalex-snapshot
Split Manufacturing Methods
inferred← citeshttps://doi.org/10.1007/978-3-030-90453-1_14openalex-snapshot
Trojan-Resilience Without Cryptography
inferred← citeshttps://doi.org/10.1007/978-3-319-14971-4_5openalex-snapshot
Fault Attacks on AES and Their Countermeasures
inferred← citeshttps://doi.org/10.1007/978-3-319-22915-7_47openalex-snapshot
Detection and Diagnosis of Hardware Trojan Using Power Analysis
inferred← citeshttps://doi.org/10.1007/978-3-319-50057-7_5openalex-snapshot
Security of Crypto IP Core: Issues and Countermeasures
inferred← citeshttps://doi.org/10.1007/978-3-319-53946-1_5openalex-snapshot
Formal Verification of Gate-Level Multiple Side Channel Parameters to Detect Hardware Trojans
inferred← citeshttps://doi.org/10.1007/978-3-319-71501-8_3openalex-snapshot
Tackling the Time-Defence: An Instruction Count Based Micro-architectural Side-Channel Attack on Block Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-642-27739-9_1712-1openalex-snapshot
Infective Countermeasure
inferred← citeshttps://doi.org/10.1007/s10836-018-5739-4openalex-snapshot
Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing
inferred← citeshttps://doi.org/10.1007/s41635-017-0021-2openalex-snapshot
An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security
inferred← citeshttps://doi.org/10.1007/s41635-017-0022-1openalex-snapshot
Two Efficient Fault-Based Attacks on CLOC and SILC
inferred← citeshttps://doi.org/10.1007/s41635-018-0049-yopenalex-snapshot
Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications
inferred← citeshttps://doi.org/10.1007/s41635-018-0060-3openalex-snapshot
IPA: an Instruction Profiling–Based Micro-architectural Side-Channel Attack on Block Ciphers
inferred← citeshttps://doi.org/10.1016/j.iot.2020.100343openalex-snapshot
Multifactor authentication scheme using physically unclonable functions
inferred← citeshttps://doi.org/10.1016/j.vlsi.2019.12.002openalex-snapshot
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge–Response pair acquisition using Built-In Self-Test before shipping
inferred← citeshttps://doi.org/10.1049/iet-ifs.2015.0399openalex-snapshot
Template attack on SPA and FA resistant implementation of Montgomery ladder
inferred← citeshttps://doi.org/10.1109/access.2016.2521727openalex-snapshot
Security Tradeoffs in Cyber Physical Systems: A Case Study Survey on Implantable Medical Devices
inferred← citeshttps://doi.org/10.1109/access.2019.2940083openalex-snapshot
Correction of Bit-Aliasing in Memristor-Based Physically Unclonable Functions With Timing Variability
inferred← citeshttps://doi.org/10.1109/csci54926.2021.00033openalex-snapshot
Securing on-Chip Communications: An On-The-Fly Encryption Architecture for SoCs
inferred← citeshttps://doi.org/10.1109/dessert.2018.8409130openalex-snapshot
The detection method of probable areas of hardware Trojans location in FPGA-based components of safety-critical systems
inferred← citeshttps://doi.org/10.1109/dessert.2019.8770055openalex-snapshot
Embedding the Digital Watermarks into FPGA-Projects Containing the Adaptive Logic Modules
inferred← citeshttps://doi.org/10.1109/edkcon56221.2022.10032935openalex-snapshot
FPGA for secured hardware & IP ownership
inferred← citeshttps://doi.org/10.1109/esscirc.2016.7598236openalex-snapshot
WSN for Machine Area Network applications
inferred← citeshttps://doi.org/10.1109/essderc.2016.7599580openalex-snapshot
WSN for Machine Area Network applications
inferred← citeshttps://doi.org/10.1109/hst.2016.7495552openalex-snapshot
Parsimonious design strategy for linear layers with high diffusion in block ciphers
inferred← citeshttps://doi.org/10.1109/ic3i44769.2018.9007281openalex-snapshot
Design And Analysis of 4-Bit Adder Using Delay-Insensitive Ternary Logic For Secure Hardware
inferred← citeshttps://doi.org/10.1109/icitsi50517.2020.9264976openalex-snapshot
First-Round and Last-Round Power Analysis Attack Against AES Devices
inferred← citeshttps://doi.org/10.1109/icm60448.2023.10378898openalex-snapshot
Real-Time Switched Capacitor Based Power Side-Channel Attack Detection
inferred← citeshttps://doi.org/10.1109/idaacs.2019.8924325openalex-snapshot
The Basic Model of Attack Resistance Estimation for Monitoring the Program Code Integrity of the FPGA-Based Systems
inferred← citeshttps://doi.org/10.1109/idaacs.2019.8924435openalex-snapshot
A Method of the Result Preparation in Addition-Based Circuits
inferred← citeshttps://doi.org/10.1109/iolts56730.2022.9897824openalex-snapshot
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11044219openalex-snapshot
Low-Clock Latency SDRR-Based AES
inferred← citeshttps://doi.org/10.1109/isqed54688.2022.9806243openalex-snapshot
BIC: Blind Identification Countermeasure for Malicious Thermal Sensor Attacks in Mobile SoCs
inferred← citeshttps://doi.org/10.1109/isqed65160.2025.11014346openalex-snapshot
Matter: Multi-Stage Adaptive Thermal Trojan for Efficiency & Resilience Degradation
inferred← citeshttps://doi.org/10.1109/mcsoc51149.2021.00039openalex-snapshot
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters
inferred← citeshttps://doi.org/10.1109/menacomm46666.2019.8988545openalex-snapshot
Device Authentication in IoT using Reconfigurable PUF
inferred← citeshttps://doi.org/10.1109/ocit65031.2024.00113openalex-snapshot
An Off-Chip Based PUF for Robust Security in FPGA Based IoT Systems
inferred← citeshttps://doi.org/10.1109/tc.2016.2603498openalex-snapshot
Binary Decision Diagram Assisted Modeling of FPGA-Based Physically Unclonable Function by Genetic Programming
inferred← citeshttps://doi.org/10.1109/tdsc.2019.2897663openalex-snapshot
On Evaluating Fault Resilient Encoding Schemes in Software
inferred← citeshttps://doi.org/10.1109/vlsid60093.2024.00091openalex-snapshot
Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers
inferred← citeshttps://doi.org/10.1109/vlsid64188.2025.00091openalex-snapshot
Novel Hardware Architectures for PRESENT Block Cipher and its FPGA Realizations
inferred← citeshttps://doi.org/10.1145/3479876.3481592openalex-snapshot
Securing network-on-chips via novel anonymous routing
inferred← citeshttps://doi.org/10.1145/3554910openalex-snapshot
Cybersecurity in India
inferred← citeshttps://doi.org/10.1145/3592798openalex-snapshot
Securing Network-on-chips Against Fault-injection and Crypto-analysis Attacks via Stochastic Anonymous Routing
inferred← citeshttps://doi.org/10.1145/3708821.3736201openalex-snapshot
N-Tracer: A Trace Driven Attack on NoC-Based MPSoC Architecture
inferred← citeshttps://doi.org/10.1145/3802584openalex-snapshot
ICBPI: Accurate and Validated Fine-Grained Power Estimation with Application to Thermal Hardware Trojan Detection and Localization in SOCs
inferred← citeshttps://doi.org/10.14569/ijacsa.2017.081018openalex-snapshot
Defense Mechanisms against Machine Learning Modeling Attacks on Strong Physical Unclonable Functions for IOT Authentication: A Review
inferred← citeshttps://doi.org/10.4218/etrij.2020-0175openalex-snapshot
Power analysis attack resilient block cipher implementation based on 1‐of‐4 data encoding
inferred← citeshttps://doi.org/10.48550/arxiv.1706.06745openalex-snapshot
Physical cryptographic primitives by chemical vapor deposition of layered MoS2
inferred← citeshttps://doi.org/10.48550/arxiv.1802.09096openalex-snapshot
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator
inferred← citeshttps://doi.org/10.48550/arxiv.1904.05141openalex-snapshot
The resistance of an FPGA implementation of Grasshopper block cipher to CPA attacks
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