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GPGCN: A General-Purpose Graph Convolution Neural Network Accelerator Based on RISC-V ISA Extension

https://doi.org/10.3390/electronics11223833

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/dac18074.2021.9586122openalex-snapshot

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks

inferredcites →https://doi.org/10.1109/dac18074.2021.9586257openalex-snapshot

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU

inferredcites →https://doi.org/10.1109/dac18074.2021.9586298openalex-snapshot

DyGNN: Algorithm and Architecture Support of Dynamic Pruning for Graph Neural Networks

inferredcites →https://doi.org/10.1109/esscirc.2014.6942056openalex-snapshot

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators

inferredcites →https://doi.org/10.1109/hpca47549.2020.00012openalex-snapshot

HyGCN: A GCN Accelerator with Hybrid Architecture

inferredcites →https://doi.org/10.1109/hpca51647.2021.00070openalex-snapshot

GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/hpca53966.2022.00041openalex-snapshot

GCoD: Graph Convolutional Network Acceleration via Dedicated Algorithm and Accelerator Co-Design

inferredcites →https://doi.org/10.1109/hpca56546.2023.10070983openalex-snapshot

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks

inferredcites →https://doi.org/10.1109/isca.2016.42openalex-snapshot

Cambricon: An Instruction Set Architecture for Neural Networks

inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot

DRAMSim2: A Cycle Accurate Memory System Simulator

inferredcites →https://doi.org/10.1109/micro50266.2020.00079openalex-snapshot

AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing

inferredcites →https://doi.org/10.1109/mm.2020.2996616openalex-snapshot

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

inferredcites →https://doi.org/10.1109/mm.2021.3061912openalex-snapshot

Compute Substrate for Software 2.0

inferredcites →https://doi.org/10.1109/tc.2020.3014632openalex-snapshot

EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks

inferredcites →https://doi.org/10.1109/tc.2022.3197083openalex-snapshot

GRIP: A Graph Neural Network Accelerator Architecture

inferredcites →https://doi.org/10.1145/3470536openalex-snapshot

ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding

inferredcites →https://doi.org/10.1145/3550075openalex-snapshot

LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator

inferredcites →https://doi.org/10.2991/assehr.k.220110.217openalex-snapshot

A Review on Important Issues in GCN Accelerator Design

inferredcites →https://doi.org/10.48550/arxiv.1706.02216openalex-snapshot

Inductive Representation Learning on Large Graphs

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.sysarc.2024.103080openalex-snapshot

Automating application-driven customization of ASIPs: A survey

inferred← citeshttps://doi.org/10.1109/access.2023.3246491openalex-snapshot

RISC-V Instruction Set Architecture Extensions: A Survey

inferred← citeshttps://doi.org/10.1109/icsp58490.2023.10248542openalex-snapshot

Design and implementation of a speech recognition module based on RISC-V embedded processor

inferred← citeshttps://doi.org/10.1109/norcas66540.2025.11231278openalex-snapshot

GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions

inferred← citeshttps://doi.org/10.1109/tcad.2025.3565470openalex-snapshot

A RISC-V Extended Infrastructure for CNNs Through Pipelined Computing and Data Dependence Optimization

inferred← citeshttps://doi.org/10.1145/3729215openalex-snapshot

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms

inferred← citeshttps://doi.org/10.1145/3735452.3735522openalex-snapshot

R-Visor: An Extensible Dynamic Binary Instrumentation and Analysis Framework for Open Instruction Set Architectures

inferred← citeshttps://doi.org/10.1145/3772277openalex-snapshot

Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support

inferred← citeshttps://doi.org/10.2139/ssrn.6225887openalex-snapshot

Inference Acceleration for Graph Convolutional Networks on RISC-V Systems

inferred← citeshttps://doi.org/10.71097/ijaidr.v14.i2.1467openalex-snapshot

Designing Neural-Network Accelerators Using RISC-V Architectures

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