On the public citation graph
Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1049/iet-cdt.2017.0163openalex-snapshot
Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms
inferredcites →https://doi.org/10.1109/acssc.2010.5757922openalex-snapshot
A PRET architecture supporting concurrent programs with composable timing properties
inferredcites →https://doi.org/10.1109/daas.2014.6842419openalex-snapshot
Improving interrupt handling in the nMPRA
inferredcites →https://doi.org/10.1109/daas.2014.6842429openalex-snapshot
Hardware event treating in nMPRA
inferredcites →https://doi.org/10.1109/daas.2016.7492553openalex-snapshot
An approach of MPRA technique over ARM cache architecture
inferredcites →https://doi.org/10.1109/eit.2012.6220705openalex-snapshot
Custom designed CPU architecture based on a hardware scheduler and independent pipeline registers — Concept and theory of operation
inferredcites →https://doi.org/10.1109/icppw.2009.21openalex-snapshot
Hardware Microkernels for Heterogeneous Manycore Systems
inferredcites →https://doi.org/10.1109/icstcc.2015.7321376openalex-snapshot
Programming paradigm of a microcontroller with hardware scheduler engine and independent pipeline registers - a software approach
inferredcites →https://doi.org/10.1109/mm.2010.78openalex-snapshot
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability
inferredcites →https://doi.org/10.1109/rtas.2014.6925994openalex-snapshot
FlexPRET: A processor platform for mixed-criticality systems
inferredcites →https://doi.org/10.1109/tc.2007.70763openalex-snapshot
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
inferredcites →https://doi.org/10.1109/tc.2014.2315637openalex-snapshot
A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems
inferredcites →https://doi.org/10.1109/tie.2009.2028359openalex-snapshot
The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator
inferredcites →https://doi.org/10.1109/tie.2012.2200214openalex-snapshot
FPGA-Based Reconfigurable Control for Fault-Tolerant Back-to-Back Converter Without Redundancy
inferredcites →https://doi.org/10.1109/tvlsi.2014.2346542openalex-snapshot
CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers
inferredcites →https://doi.org/10.1145/1119772.1119925openalex-snapshot
A comparison of the RTU hardware RTOS with a hardware/software RTOS
inferredcites →https://doi.org/10.1145/1278480.1278545openalex-snapshot
The case for the precision timed (PRET) machine
inferredcites →https://doi.org/10.3390/electronics4041062openalex-snapshot
Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs
inferredcites →https://doi.org/10.3390/electronics7090205openalex-snapshot
Real-Time Embedded Systems: Present and Future
inferredcites →https://doi.org/10.3390/electronics8010052openalex-snapshot
Hardware-Enhanced Protection for the Runtime Data Security in Embedded Systems
inferredcites →https://doi.org/10.4316/aece.2016.04007openalex-snapshot
Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-023-05151-0openalex-snapshot
FPGA implementation of hardware accelerated RTOS based on real-time event handling
inferred← citeshttps://doi.org/10.1007/s40435-020-00737-5openalex-snapshot
A review on drones controlled in real-time
inferred← citeshttps://doi.org/10.1109/cjece.2020.3005360openalex-snapshot
Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation
inferred← citeshttps://doi.org/10.1109/das49615.2020.9108930openalex-snapshot
Improving the performance of Real-Time Event Processing based on Preemptive Scheduler FPGA Implementation
inferred← citeshttps://doi.org/10.1109/das69882.2026.11553351openalex-snapshot
A RISC-V Pipeline Simulation Framework for Comparative Evaluation of nMPRA and nHSE Real-Time Microarchitectures
inferred← citeshttps://doi.org/10.1145/3386164.3386175openalex-snapshot
Hardware Scheduler Implementation based on Replicated Resource Architecture for Reconfigurable Systems
inferred← citeshttps://doi.org/10.3390/computers9010015openalex-snapshot
Design, Fabrication, and Testing of an IoT Healthcare Cardiac Monitoring Device
inferred← citeshttps://doi.org/10.3390/electronics8070789openalex-snapshot
Task Scheduling to Constrain Peak Current Consumption in Wearable Healthcare Sensors
inferred← citeshttps://doi.org/10.3390/electronics9111789openalex-snapshot
New Applications and Architectures Based on FPGA/SoC
inferred← citeshttps://doi.org/10.3390/math10152637openalex-snapshot
Designing a Custom CPU Architecture Based on Hardware RTOS and Dynamic Preemptive Scheduler
inferred← citeshttps://doi.org/10.3390/s21134500openalex-snapshot
An Overview of the nMPRA and nHSE Microarchitectures for Real-Time Applications
inferred← citeshttps://doi.org/10.4316/aece.2020.01009openalex-snapshot
Hardware Real-time Event Management with Support of RISC-V Architecture for FPGA-Based Reconfigurable Embedded Systems
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