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Time-critical computing on a single-chip massively parallel processor

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Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
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Ensuring Consistency between Cycle-Accurate and Instruction Set Simulators
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Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture
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Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs
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Static Probabilistic Timing Analysis for Multi-path Programs
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Speculative Execution and Timing Predictability in an Open Source RISC-V Core
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A dependency-graph based priority assignment algorithm for real-time traffic over NoCs with shared virtual-channels
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Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures
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Mapping Method Usable with Clustered Many-core Platforms for Simulink Model
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Near-optimal deployment of dataflow applications on many-core platforms with real-time guarantees
inferred← citeshttps://doi.org/10.23919/date.2019.8714926openalex-snapshot
Scratchpad Memories with Ownership
inferred← citeshttps://doi.org/10.23919/date48585.2020.9116230openalex-snapshot
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Minimising shared resource contention when scheduling real-time applications on multi-core architectures
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