On the public citation graph
PerfPred: A web‐based tool for exploring computer architecture design space
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/s11227-006-0010-7openalex-snapshot
Binary Decision Diagrams and neural networks
inferredcites →https://doi.org/10.1016/0096-0551(85)90019-0openalex-snapshot
Structured computer organization
inferredcites →https://doi.org/10.1016/0165-6074(88)90045-2openalex-snapshot
An animated simulation environment for microprocessors
inferredcites →https://doi.org/10.1016/0360-1315(84)90016-2openalex-snapshot
An interactive modelling system to assist the teaching of computer architecture
inferredcites →https://doi.org/10.1016/c2013-0-08305-3openalex-snapshot
Computer Organization and Design
inferredcites →https://doi.org/10.1016/j.eswa.2007.04.010openalex-snapshot
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling
inferredcites →https://doi.org/10.1016/j.eswa.2007.09.052openalex-snapshot
Investigating data preprocessing methods for circuit complexity models
inferredcites →https://doi.org/10.1016/s0141-9331(01)00111-9openalex-snapshot
An educational tool for testing caches on symmetric multiprocessors
inferredcites →https://doi.org/10.1109/2.982915openalex-snapshot
Rsim: simulating shared-memory multiprocessors with ILP processors
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/4.148323openalex-snapshot
An analytical access time model for on-chip cache memories
inferredcites →https://doi.org/10.1109/71.689444openalex-snapshot
Modeled and measured instruction fetching performance for superscalar microprocessors
inferredcites →https://doi.org/10.1109/ecbs.1996.494568openalex-snapshot
WinDLX and MIPSim pipeline simulators for teaching computer architecture
inferredcites →https://doi.org/10.1109/fie.2002.1158742openalex-snapshot
The educational range of visual simulations of the Little Man Computer architecture paradigm
inferredcites →https://doi.org/10.1109/icecs.2006.379732openalex-snapshot
Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network
inferredcites →https://doi.org/10.1109/inmic.2006.358161openalex-snapshot
Using Recurrent Neural Networks for Circuit Complexity Modeling
inferredcites →https://doi.org/10.1109/mwscas.2007.4488692openalex-snapshot
A methodology for evaluation time approximation
inferredcites →https://doi.org/10.1109/mwscas.2007.4488749openalex-snapshot
Predicting processor performance with a machine learnt model
inferredcites →https://doi.org/10.1109/te.2004.842918openalex-snapshot
Flexible Web-Based Educational System for Teaching Computer Architecture and Organization
inferredcites →https://doi.org/10.1142/s0218126607003940openalex-snapshot
MODELING OF TRACE- AND BLOCK-BASED CACHES
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1275462.1275492openalex-snapshot
A survey of web resources for teaching computer architecture
inferredcites →https://doi.org/10.1145/192724.192730openalex-snapshot
Theoretical modeling of superscalar processor performance
inferredcites →https://doi.org/10.1145/563340.563408openalex-snapshot
Teaching computer organization/architecture with limited resources using simulators
inferredcites →https://doi.org/10.1145/563517.563408openalex-snapshot
Teaching computer organization/architecture with limited resources using simulators
inferredcites →https://doi.org/10.5281/zenodo.1334446openalex-snapshot
Learning Monte Carlo Data For Circuit Path Length
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cae.20317openalex-snapshot
MNEME: A memory hierarchy simulator for an engineering computer architecture course
inferred← citeshttps://doi.org/10.1002/cae.20537openalex-snapshot
Personal Learning Environment Box (PLEBOX): A new approach to E‐learning platforms
inferred← citeshttps://doi.org/10.1002/cae.21600openalex-snapshot
A web‐based method for building and simulating standard cell circuits—A classroom application
inferred← citeshttps://doi.org/10.1002/cae.21681openalex-snapshot
Incorporating hardware and software features into a prediction model for processor‐system throughput
inferred← citeshttps://doi.org/10.1007/978-90-481-3177-8_4openalex-snapshot
A Reduced-Dimension Processor Model
inferred← citeshttps://doi.org/10.1109/citisia.2009.5224239openalex-snapshot
Analyzing sensitivity of code execution efficiency to software and hardware parameters
inferred← citeshttps://doi.org/10.1109/isda.2012.6416643openalex-snapshot
A neural model for processor-throughput using hardware parameters and software's dynamic behavior
inferred← citeshttps://doi.org/10.1145/2325296.2325396openalex-snapshot
A hardware simulator for teaching CPU design
inferred← citeshttps://doi.org/10.14742/ajet.4704openalex-snapshot
The conceptualisation of cognitive tools in learning and technology: A review
inferred← citeshttps://doi.org/10.4018/978-1-4666-0936-5.ch002openalex-snapshot
A Mobile Learning Content-independent Versatile Ubiquitous System (CiVUS)
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