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Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Strong Authentication for RFID Systems Using the AES Algorithm
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Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004, Proceedings
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A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
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Examining smart-card security under the threat of power analysis attacks
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Differential Power Analysis resistance of Camellia and countermeasure strategy on FPGAs
inferred← citeshttps://doi.org/10.1109/fpt.2010.5681790openalex-snapshot
Lightweight DPA resistant solution on FPGA to counteract power models
inferred← citeshttps://doi.org/10.1109/fpt.2013.6718347openalex-snapshot
TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs
inferred← citeshttps://doi.org/10.1109/gcce.2017.8229302openalex-snapshot
Security evaluation of cryptographic modules against side-channel attack using a biased data set
inferred← citeshttps://doi.org/10.1109/host55118.2023.10133813openalex-snapshot
Low-Latency Masking with Arbitrary Protection Order Based on Click Elements
inferred← citeshttps://doi.org/10.1109/hpec.2015.7322469openalex-snapshot
Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs
inferred← citeshttps://doi.org/10.1109/hst.2008.4559041openalex-snapshot
Slicing up a perfect hardware masking scheme
inferred← citeshttps://doi.org/10.1109/hst.2008.4559042openalex-snapshot
Place-and-route impact on the security of DPL designs in FPGAs
inferred← citeshttps://doi.org/10.1109/hst.2010.5513113openalex-snapshot
ExCCel: Exploration of complementary cells for efficient DPA attack resistivity
inferred← citeshttps://doi.org/10.1109/hst.2014.6855564openalex-snapshot
Side-channel leakage on silicon substrate of CMOS cryptographic chip
inferred← citeshttps://doi.org/10.1109/hst.2015.7140250openalex-snapshot
Simulation and analysis of negative-bias temperature instability aging on power analysis attacks
inferred← citeshttps://doi.org/10.1109/hst.2018.8383911openalex-snapshot
On state encoding against power analysis attacks for finite state controllers
inferred← citeshttps://doi.org/10.1109/icaacca51523.2021.9465337openalex-snapshot
Side Channel Attack Countermeasure for Low Power Devices with AES Encryption
inferred← citeshttps://doi.org/10.1109/iccd.2018.00012openalex-snapshot
Composable Template Attacks Using Templates for Individual Architectural Components
inferred← citeshttps://doi.org/10.1109/icceet.2012.6203865openalex-snapshot
Design of Delay Based Dual Rail Precharge Logic to reduce DPA attacks
inferred← citeshttps://doi.org/10.1109/iccpct.2016.7530142openalex-snapshot
CALPAN: Countermeasure against Leakage Power Analysis attack by normalized DDPL
inferred← citeshttps://doi.org/10.1109/icecet58911.2023.10389410openalex-snapshot
Reusing Outputs from S-Boxes for Tamper Resistant Design
inferred← citeshttps://doi.org/10.1109/icecs.2009.5410774openalex-snapshot
Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA
inferred← citeshttps://doi.org/10.1109/icecs.2009.5410921openalex-snapshot
Delay-based dual-rail pre-charge logic
inferred← citeshttps://doi.org/10.1109/icet51757.2021.9450907openalex-snapshot
Implementation of SM4 Based on Random State to Resist DPA
inferred← citeshttps://doi.org/10.1109/icics.2009.5397727openalex-snapshot
A new remote keyless entry system resistant to power analysis attacks
inferred← citeshttps://doi.org/10.1109/icm.2010.5696147openalex-snapshot
An improved differential pull-down network logic configuration for DPA resistant circuits
inferred← citeshttps://doi.org/10.1109/icscs.2009.5412599openalex-snapshot
Overview of Dual rail with Precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors
inferred← citeshttps://doi.org/10.1109/icscs.2009.5412604openalex-snapshot
Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher
inferred← citeshttps://doi.org/10.1109/icsss.2013.6623020openalex-snapshot
An energy recovery logic level countermeasure for power analysis attacks on AES
inferred← citeshttps://doi.org/10.1109/idt.2014.7038597openalex-snapshot
Impact analysis of resistive bridge within deep submicron Secured CMOS circuits
inferred← citeshttps://doi.org/10.1109/imtc.2011.5944288openalex-snapshot
FPGA-based measurement and evaluation of power analysis attack resistant asynchronous S-Box
inferred← citeshttps://doi.org/10.1109/ipdps.2009.5161204openalex-snapshot
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs
inferred← citeshttps://doi.org/10.1109/ipdps.2011.142openalex-snapshot
Hyperelliptic Curve Cryptoarchitecture for Fast Execution of Schnorr and Okamoto Authentication Protocols
inferred← citeshttps://doi.org/10.1109/isca.2018.00059openalex-snapshot
Hiding Intermittent Information Leakage with Architectural Support for Blinking
inferred← citeshttps://doi.org/10.1109/iscas.2006.1693233openalex-snapshot
Side Channel Analysis Resistant Design Flow
inferred← citeshttps://doi.org/10.1109/iscas.2006.1693234openalex-snapshot
Implementation Aspects of the DPA-Resistant Logic Style MDPL
inferred← citeshttps://doi.org/10.1109/iscas.2008.4541402openalex-snapshot
Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems
inferred← citeshttps://doi.org/10.1109/iscas.2008.4542134openalex-snapshot
Utilizing sub-threshold technology for the creation of secure circuits
inferred← citeshttps://doi.org/10.1109/iscas.2017.8050749openalex-snapshot
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer
inferred← citeshttps://doi.org/10.1109/iscas.2018.8351456openalex-snapshot
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach
inferred← citeshttps://doi.org/10.1109/iscas48785.2022.9937684openalex-snapshot
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations
inferred← citeshttps://doi.org/10.1109/iscas58744.2024.10557893openalex-snapshot
A Light-weight and Tamper-resistant AES Implementation by FPGAs
inferred← citeshttps://doi.org/10.1109/iscit57293.2023.10376105openalex-snapshot
Effect of High Frequency Noise Using DCMs in FPGA on Power Analysis Attack
inferred← citeshttps://doi.org/10.1109/ised.2010.20openalex-snapshot
An Energy Efficient Secure Logic to Provide Resistance against Differential Power Analysis Attacks
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Enhancing reactive countermeasure against EM attacks with low overhead
inferred← citeshttps://doi.org/10.1109/isias.2011.6122844openalex-snapshot
Enhance hardware security using FIFO in pipelines
inferred← citeshttps://doi.org/10.1109/isie.2011.145openalex-snapshot
A Comprehensive Design Method Based on WDDL and Dynamic Cryptosystem to Resist DPA Attack
inferred← citeshttps://doi.org/10.1109/ispacs.2011.6146067openalex-snapshot
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card
inferred← citeshttps://doi.org/10.1109/isqed.2009.4810376openalex-snapshot
Charge recovery logic as a side channel attack countermeasure
inferred← citeshttps://doi.org/10.1109/isqed.2015.7085468openalex-snapshot
Side channel attacks in embedded systems: A tale of hostilities and deterrence
inferred← citeshttps://doi.org/10.1109/isvlsi.2012.68openalex-snapshot
RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA)
inferred← citeshttps://doi.org/10.1109/isvlsi.2016.121openalex-snapshot
LLPA: Logic State Based Leakage Power Analysis
inferred← citeshttps://doi.org/10.1109/isvlsi.2017.44openalex-snapshot
Secured-by-Design FPGA against Early Evaluation
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00064openalex-snapshot
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility
inferred← citeshttps://doi.org/10.1109/itng.2009.184openalex-snapshot
A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m)
inferred← citeshttps://doi.org/10.1109/itng.2009.185openalex-snapshot
A New Method to Reduce the Side-Channel Leakage Caused by Unbalanced Capacitances of Differential Interconnections in Dual-Rail Logic Styles
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[2010] Avoiding Side-Channel Attacks in Embedded Systems with Non-deterministic Branches
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