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Successfully Attacking Masked AES Hardware Implementations
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11502760_28openalex-snapshot
A Side-Channel Analysis Resistant Description of the AES S-Box
inferredcites →https://doi.org/10.1007/11506447_10openalex-snapshot
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
inferredcites →https://doi.org/10.1007/11545262openalex-snapshot
Cryptographic hardware and embedded systems - CHES 2005 : 7th International Workshop, Edinburgh, UK, August 29-September 1, 2005 : proceedings
inferredcites →https://doi.org/10.1007/11545262_13openalex-snapshot
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
inferredcites →https://doi.org/10.1007/11545262_14openalex-snapshot
Masking at Gate Level in the Presence of Glitches
inferredcites →https://doi.org/10.1007/3-540-36400-5openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2002
inferredcites →https://doi.org/10.1007/3-540-36400-5_15openalex-snapshot
Simplified Adaptive Multiplicative Masking for AES
inferredcites →https://doi.org/10.1007/3-540-36400-5_16openalex-snapshot
Multiplicative Masking and Power Analysis of AES
inferredcites →https://doi.org/10.1007/3-540-44499-8openalex-snapshot
Cryptographic Hardware and Embedded Systems — CHES 2000
inferredcites →https://doi.org/10.1007/3-540-44499-8_19openalex-snapshot
Using Second-Order Power Analysis to Attack DPA Resistant Software
inferredcites →https://doi.org/10.1007/3-540-44709-1openalex-snapshot
Cryptographic Hardware and Embedded Systems — CHES 2001
inferredcites →https://doi.org/10.1007/3-540-44709-1_26openalex-snapshot
An Implementation of DES and AES, Secure against Some Attacks
inferredcites →https://doi.org/10.1007/3-540-45537-x_10openalex-snapshot
Polynomial Reconstruction Based Cryptography
inferredcites →https://doi.org/10.1007/3-540-45760-7openalex-snapshot
Topics in Cryptology — CT-RSA 2002
inferredcites →https://doi.org/10.1007/3-540-45760-7_6openalex-snapshot
An ASIC Implementation of the AES SBoxes
inferredcites →https://doi.org/10.1007/3-540-48405-1openalex-snapshot
Advances in Cryptology — CRYPTO’ 99
inferredcites →https://doi.org/10.1007/978-3-540-25937-4_21openalex-snapshot
Two Power Analysis Attacks against One-Mask Methods
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_1openalex-snapshot
Towards Efficient Second-Order Power Analysis
inferredcites →https://doi.org/10.1007/978-3-540-30564-4_5openalex-snapshot
Provably Secure Masking of AES
inferredcites →https://doi.org/10.1007/978-3-540-30574-3_24openalex-snapshot
Side-Channel Leakage of Masked CMOS Gates
inferredcites →https://doi.org/10.1007/b99451openalex-snapshot
Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004, Proceedings
inferredcites →https://doi.org/10.1109/itcc.2004.1286711openalex-snapshot
Power-analysis attack on an ASIC AES implementation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/cta.2296openalex-snapshot
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
inferred← citeshttps://doi.org/10.1007/11894063_19openalex-snapshot
Three-Phase Dual-Rail Pre-charge Logic
inferred← citeshttps://doi.org/10.1007/11894063_20openalex-snapshot
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
inferred← citeshttps://doi.org/10.1007/11894063_21openalex-snapshot
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
inferred← citeshttps://doi.org/10.1007/11894063_7openalex-snapshot
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
inferred← citeshttps://doi.org/10.1007/11935308_38openalex-snapshot
Threshold Implementations Against Side-Channel Attacks and Glitches
inferred← citeshttps://doi.org/10.1007/978-1-4614-7915-4_9openalex-snapshot
A Survey of Recent Results in FPGA Security and Intellectual Property Protection
inferred← citeshttps://doi.org/10.1007/978-3-030-41579-2_17openalex-snapshot
Practical Evaluation Methodology of Higher-Order Maskings at Different Operating Frequencies
inferred← citeshttps://doi.org/10.1007/978-3-030-41702-4_5openalex-snapshot
Monomial Evaluation of Polynomial Functions Protected by Threshold Implementations
inferred← citeshttps://doi.org/10.1007/978-3-030-64837-4_27openalex-snapshot
Cryptanalysis of Masked Ciphers: A Not So Random Idea
inferred← citeshttps://doi.org/10.1007/978-3-030-92518-5_10openalex-snapshot
Analyzing Masked Ciphers Against Transition and Coupling Effects
inferred← citeshttps://doi.org/10.1007/978-3-031-19185-5_18openalex-snapshot
Side-Channel Protection in Cryptographic Hardware
inferred← citeshttps://doi.org/10.1007/978-3-031-22829-2_2openalex-snapshot
Light but Tight: Lightweight Composition of Serialized S-Boxes with Diffusion Layers for Strong Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-031-26553-2_18openalex-snapshot
Higher-Order Masking Scheme for Trivium Hardware Implementation
inferred← citeshttps://doi.org/10.1007/978-3-031-30634-1_20openalex-snapshot
Effective and Efficient Masking with Low Noise Using Small-Mersenne-Prime Ciphers
inferred← citeshttps://doi.org/10.1007/978-3-032-01806-9_6openalex-snapshot
Leveled Software Implementation of Polka and Comparison with Uniformly Masked Kyber
inferred← citeshttps://doi.org/10.1007/978-3-032-31130-6_9openalex-snapshot
Can We Tolerate Small Side-Channel Leakages: The Role of Registers in Glitch-Stopping Circuits
inferred← citeshttps://doi.org/10.1007/978-3-032-35415-0_11openalex-snapshot
A Formal Security Proof of Masking
inferred← citeshttps://doi.org/10.1007/978-3-319-02726-5_18openalex-snapshot
Comprehensive Evaluation of AES Dual Ciphers as a Side-Channel Countermeasure
inferred← citeshttps://doi.org/10.1007/978-3-319-03515-4_14openalex-snapshot
On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective
inferred← citeshttps://doi.org/10.1007/978-3-319-03584-0_33openalex-snapshot
An Improved Differential Fault Analysis Attack to AES Using Reduced Searching Space
inferred← citeshttps://doi.org/10.1007/978-3-319-04852-9_11openalex-snapshot
Hardware Implementation and Side-Channel Analysis of Lapin
inferred← citeshttps://doi.org/10.1007/978-3-319-06734-6_15openalex-snapshot
Minimizing S-Boxes in Hardware by Utilizing Linear Transformations
inferred← citeshttps://doi.org/10.1007/978-3-319-06734-6_17openalex-snapshot
A More Efficient AES Threshold Implementation
inferred← citeshttps://doi.org/10.1007/978-3-319-06734-6_25openalex-snapshot
DRECON: DPA Resistant Encryption by Construction
inferred← citeshttps://doi.org/10.1007/978-3-319-07536-5_20openalex-snapshot
Detecting Hidden Leakages
inferred← citeshttps://doi.org/10.1007/978-3-319-10175-0_10openalex-snapshot
Collision-Correlation Attack Against a First-Order Masking Scheme for MAC Based on SHA-3
inferred← citeshttps://doi.org/10.1007/978-3-319-12160-4_6openalex-snapshot
Enabling 3-Share Threshold Implementations for all 4-Bit S-Boxes
inferred← citeshttps://doi.org/10.1007/978-3-319-13039-2_20openalex-snapshot
Wire-Tap Codes as Side-Channel Countermeasure
inferred← citeshttps://doi.org/10.1007/978-3-319-21356-9_6openalex-snapshot
Higher-Order Glitch Resistant Implementation of the PRESENT S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-21476-4_7openalex-snapshot
Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware
inferred← citeshttps://doi.org/10.1007/978-3-319-24126-5_10openalex-snapshot
S-boxes, Boolean Functions and Codes for the Resistance of Block Ciphers to Cryptographic Attacks, with or without Side Channels
inferred← citeshttps://doi.org/10.1007/978-3-319-28166-7_27openalex-snapshot
Arithmetic Addition over Boolean Masking
inferred← citeshttps://doi.org/10.1007/978-3-319-31271-2_16openalex-snapshot
Higher-Order Threshold Implementation of the AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-49025-0_8openalex-snapshot
A Novel Mutating Runtime Architecture for Embedding Multiple Countermeasures Against Side-Channel Attacks
inferred← citeshttps://doi.org/10.1007/978-3-319-49445-6_21openalex-snapshot
A Methodology for the Characterisation of Leakages in Combinatorial Logic
inferred← citeshttps://doi.org/10.1007/978-3-319-51966-1_23openalex-snapshot
Towards Side-Channel Secure Firmware Updates
inferred← citeshttps://doi.org/10.1007/978-3-319-55589-8_3openalex-snapshot
Codes for Side-Channel Attacks and Protections
inferred← citeshttps://doi.org/10.1007/978-3-319-56620-7_19openalex-snapshot
Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model
inferred← citeshttps://doi.org/10.1007/978-3-319-64647-3_4openalex-snapshot
Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation
inferred← citeshttps://doi.org/10.1007/978-3-319-66787-4_30openalex-snapshot
Very High Order Masking: Efficient Implementation and Security Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-319-70694-8_26openalex-snapshot
The First Thorough Side-Channel Hardware Trojan
inferred← citeshttps://doi.org/10.1007/978-3-319-71667-1_20openalex-snapshot
Several Masked Implementations of the Boyar-Peralta AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-319-89641-0_3openalex-snapshot
On Masked Galois-Field Multiplication for Authenticated Encryption Resistant to Side Channel Analysis
inferred← citeshttps://doi.org/10.1007/978-3-319-89641-0_5openalex-snapshot
Micro-architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors
inferred← citeshttps://doi.org/10.1007/978-3-319-99073-6_10openalex-snapshot
Combination of Hardware and Software: An Efficient AES Implementation Resistant to Side-Channel Attacks on All Programmable SoC
inferred← citeshttps://doi.org/10.1007/978-3-540-68164-9_15openalex-snapshot
Yet Another Attack on Vest
inferred← citeshttps://doi.org/10.1007/978-3-540-68914-0_27openalex-snapshot
A Very Compact “Perfectly Masked” S-Box for AES
inferred← citeshttps://doi.org/10.1007/978-3-540-74735-2_8openalex-snapshot
DPA-Resistance Without Routing Constraints?
inferred← citeshttps://doi.org/10.1007/978-3-540-76788-6_21openalex-snapshot
Power Analysis Attacks on MDPL and DRSL Implementations
inferred← citeshttps://doi.org/10.1007/978-3-540-77026-8_29openalex-snapshot
Design of a Differential Power Analysis Resistant Masked AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-540-77048-0_17openalex-snapshot
Compact and Secure Design of Masked AES S-Box
inferred← citeshttps://doi.org/10.1007/978-3-540-77086-2_7openalex-snapshot
A Near Optimal S-Box Design
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Differential Power Analysis of HMAC Based on SHA-2, and Countermeasures
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On the BRIP Algorithms Security for RSA
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A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
inferred← citeshttps://doi.org/10.1007/978-3-540-85174-5_12openalex-snapshot
On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoq Code Hopping Scheme
inferred← citeshttps://doi.org/10.1007/978-3-540-85886-7_24openalex-snapshot
Comparative Evaluation of Rank Correlation Based DPA on an AES Prototype Chip
inferred← citeshttps://doi.org/10.1007/978-3-540-89985-3_81openalex-snapshot
On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices
inferred← citeshttps://doi.org/10.1007/978-3-540-95948-9_34openalex-snapshot
Differential Capacitance Analysis
inferred← citeshttps://doi.org/10.1007/978-3-642-00730-9_14openalex-snapshot
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
inferred← citeshttps://doi.org/10.1007/978-3-642-00862-7_29openalex-snapshot
Fault Analysis Attack against an AES Prototype Chip Using RSL
inferred← citeshttps://doi.org/10.1007/978-3-642-14423-3_11openalex-snapshot
Power Analysis of Single-Rail Storage Elements as Used in MDPL
inferred← citeshttps://doi.org/10.1007/978-3-642-14992-4_7openalex-snapshot
Lightweight Cryptography and DPA Countermeasures: A Survey
inferred← citeshttps://doi.org/10.1007/978-3-642-15031-9_28openalex-snapshot
Provably Secure Higher-Order Masking of AES
inferred← citeshttps://doi.org/10.1007/978-3-642-15031-9_9openalex-snapshot
Correlation-Enhanced Power Analysis Collision Attack
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On Side-Channel Resistant Block Cipher Usage
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Pushing the Limits: A Very Compact and a Threshold Implementation of AES
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Leakage Squeezing Countermeasure against High-Order Attacks
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Generic Side-Channel Distinguishers: Improvements and Limitations
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Improved Collision-Correlation Power Analysis on First Order Protected AES
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PKDPA: An Enhanced Probabilistic Differential Power Attack Methodology
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Implementation and Evaluation of an SCA-Resistant Embedded Processor
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An Exploration of the Kolmogorov-Smirnov Test as a Competitor to Mutual Information Analysis
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A High-Performance Implementation of Differential Power Analysis on Graphics Cards
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Statistical Tools Flavor Side-Channel Collision Attacks
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Threshold Implementations of All 3 ×3 and 4 ×4 S-Boxes
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How Far Should Theory Be from Practice?
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Higher-Order Masking Schemes for S-Boxes
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Chosen-IV Correlation Power Analysis on KCipher-2 and a Countermeasure
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On the Simplicity of Converting Leakages from Multivariate to Univariate
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Profiling DPA: Efficacy and Efficiency Trade-Offs
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Does My Device Leak Information? An a priori Statistical Power Analysis of Leakage Detection Tests
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Gate-Level Masking under a Path-Based Leakage Metric
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Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
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Higher-Order Threshold Implementations
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Transient-Steady Effect Attack on Block Ciphers
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Assessment of Hiding the Higher-Order Leakages in Hardware
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Polynomial Evaluation and Side Channel Analysis
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Towards Sound Fresh Re-keying with Hard (Physical) Learning Problems
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ParTI – Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks
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Masking AES with $$d+1$$ Shares in Hardware
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Faster Evaluation of SBoxes via Common Shares
inferred← citeshttps://doi.org/10.1007/978-3-662-53140-2_9openalex-snapshot
Strong 8-bit Sboxes with Efficient Masking in Hardware
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Unknown-Input Attacks in the Parallel Setting: Improving the Security of the CHES 2012 Leakage-Resilient PRF
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Hardware Security Features for Secure Embedded Devices
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Differential Power Analysis: Attacks and Resisting Techniques
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Compact and Secure S-Box Implementations of AES—A Review
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ProverNG: Efficient Verification of Compositional Masking for Cryptosystem’s Side-Channel Security
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New First-Order Secure AES Implementation Without Online Fresh Randomness Records
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IP Masking with Generic Security Guarantees Under Minimum Assumptions, and Applications
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Breaking Masked Kyber: ResNet-Based Masked Kyber Share Recovery Method
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Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches
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Side-Channel Resistant Crypto for Less than 2,300 GE
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Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version
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Path switching: a technique to tolerate dual rail routing imbalances
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AES side-channel countermeasure using random tower field constructions
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Hadamard matrices, d-linearly independent sets and correlation-immune Boolean functions with minimum Hamming weights
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A further study on bridge structures and constructing bijective S-boxes for low-latency masking
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Non-complete set coverings for higher order threshold implementations
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Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard
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Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs
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Side-channel analysis attacks based on deep learning network
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Design of differential power analysis resistant crypto chip based on time randomization
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Protecting lightweight block cipher implementation in mobile big data computing
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Threshold implementations of small S-boxes
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Masking and leakage-resilient primitives: One, the other(s) or both?
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Monomial evaluation of polynomial functions protected by threshold implementations—with an illustration on AES—
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A fair evaluation framework for comparing side-channel distinguishers
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Strong 8-bit Sboxes with efficient masking in hardware extended version
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Deep learning for side-channel analysis and introduction to ASCAD database
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IPM-RED: combining higher-order masking with robust error detection
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Reducing risks through simplicity: high side-channel security for lazy engineers
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SPSA: Semi-Permanent Stuck-At fault analysis of AES Rijndael SBox
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A Methodology for the Characterisation of Leakages in Combinatorial Logic
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Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
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On Testing Embedded Software
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Dual-rail transition logic: A logic style for counteracting power analysis attacks
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Side-channel information leakage analysis and countermeasures in an embedded CPU microarchitecture
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Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level
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High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation
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The implementation of ring oscillator based PUF designs in Field Programmable Gate Arrays using of different challenge
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Efficient DPA side channel countermeasure with MIM capacitors-based current equalizer
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Vulnerability modeling of cryptographic hardware to power analysis attacks
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Several weaknesses of the implementation for the theoretically secure masking schemes under ISW framework
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A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs
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Dynamic inhomogeneous S-Boxes design for efficient AES masking mechanisms
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Side channel analysis of an automotive microprocessor
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New second‐order threshold implementation of AES
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Effect of glitches against masked AES S-box implementation and countermeasure
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Secure and Efficient Masking of Lightweight Ciphers in Software and Hardware
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An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
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Multi-Byte Power Analysis: A Generic Approach Based on Linear Regression
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Reading It like an Open Book: Single-trace Blind Side-channel Attacks on Garbled Circuit Frameworks
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Accurate ICMP TraceBack Model under DoS/DDoS Attack
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Preventing the Side-Channel Leakage of Masked AES S-Box
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SMASh: A State Encoding Methodology Against Attacks on Finite State Machines
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A combinational power analysis method against cryptographic hardware
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Enhanced side-channel leakage detection method by considering combinational logic
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Template Attack Against AES in Counter Mode With Unknown Initial Counter
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Design and Implementation of Compact AES-128 Core with Folded Datapath and Control-Driven Use
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A New Fast and Side-Channel Resistant AES Hardware Architecture
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GLiTCH: GLiTCH induced Transitions for Secure Crypto-Hardware
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Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers
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A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
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Implementation of a Boolean Masking Scheme for the SCREAM Cipher
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Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures
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Differential power analysis of AES ASIC implementations with various S-box circuits
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Power Analysis on RSM Schemes in Cryptographic Chips
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Current Consumption Modeling of Logic Cells Based on Measurements for Side-channel Attack Simulation
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Countermeasures Against Branch Target Buffer Attacks
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Passive and Active Combined Attacks: Combining Fault Attacks and Side Channel Analysis
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WDDL is Protected against Setup Time Violation Attacks
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Passive and Active Combined Attacks on AES Combining Fault Attacks and Side Channel Analysis
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Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI
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More Efficient Private Circuits II through Threshold Implementations
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Glitch-Resistant Masking Schemes as Countermeasure Against Fault Sensitivity Analysis
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Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic
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On reconfigurable fabrics and generic side-channel countermeasures
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Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption
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Automated Masking of FPGA-Mapped Designs
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FPGA Implementation and Analysis of Random Delay Insertion Countermeasure against DPA
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Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs
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RS-Mask: Random Space Masking as an Integrated Countermeasure against Power and Fault Analysis
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Low-Latency Masking with Arbitrary Protection Order Based on Click Elements
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Security Aspects of Masking on FPGAs
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Place-and-route impact on the security of DPL designs in FPGAs
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Early feedback on side-channel risks with accelerated toggle-counting
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Practical evaluation of DPA countermeasures on reconfigurable hardware
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Glitch-free implementation of masking in modern FPGAs
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Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs
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Extracting Side-Channel Leakage from Round Unrolled Implementations of Lightweight Ciphers
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On the importance of protecting personal information privacy: A lightweight and portable implementation of cryptographic systems
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Power Analysis on SM4 with Boosting Methods
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Power analysis of a FPGA implementation of SM4
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Advanced modes in AES: Are they safe from power analysis based side channel attacks?
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Delay-based dual-rail pre-charge logic
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A new remote keyless entry system resistant to power analysis attacks
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Coupling aware energy-efficient data scrambling on memory-processor interfaces
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A Lightweight Countermeasure of SM4 against Side Channel Analysis
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Correlated power noise generator as a low cost DPA countermeasures to secure hardware AES cipher
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Side Channel Analysis Resistant Design Flow
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Advanced Encryption Standard (AES) implementation with increased DPA resistance and low overhead
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An area-efficient shuffling scheme for AES implementation on FPGA
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DPA vulnerability analysis on Trivium stream cipher using an optimized power model
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DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer
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Horizontal Correlation Analysis without Precise Location on Schoolbook Polynomial Multiplication of Lattice-based Cryptosystem
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Normalized Differential Power Analysis - for Ghost Peaks Mitigation
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